View MAX9880AETMT_8746823.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the max9880a is a high-performance, stereo audiocodec designed for portable consumer applications such as smartphones and tablets. operating from a sin- gle 1.8v supply to ensure low-power consumption, the max9880a offers a variety of input and output configu- rations for design flexibility. the max9880a can be combined with an audio subsystem, such as the max9877 or max9879, for a complete audio solution for portable applications. the max9880a? stereo differential microphone inputs can support either analog or digital microphones. a stereo single-ended line input, with a configurable pre- amplifier, can either be recorded by the adc or routed directly to the headphone or line output amplifiers. the stereo headphone amplifiers can be configured as dif- ferential, single ended, or capacitorless. the stereo line outputs have dedicated level adjustment. there are two digital audio interfaces. the primary interface is intended for voiceband applications, while the secondary interface can be used for high perfor- mance stereo audio data. two digital input streams can be processed simultaneously and both digital inter- faces support tdm and i 2 s data formats. the flexible clocking circuitry utilizes any available10mhz to 60mhz system clock, eliminating the need for an external pll and multiple crystal oscillators. both the adc and dac can be operated synchronously or asynchronously in master or slave mode. the adc can be operated from 8khz to 48khz sample rates, while the dac can be operated up to 96khz. the max9880a prevents click and pop during volume changes and during power-up and power-down. audio quality is further enhanced with user-configurable digital filters for voice and audio data. voiceband filters pro- vide extra attenuation at the gsm packet frequency and greater than 70db stopband attenuation at f s /2. an i 2 c or spi serial interface provides control for volume lev-els, signal mixing, and general operating modes. the max9880a is available in space-saving, 48-bump, 2.7mm x 3.5mm, 0.4mm-pitch wlp and 48-pin, 6mm x 6mm tqfn packages. applications cellular phonestablet pcs portable gaming devices portable multimedia players features ? 1.8v single-supply operation ? 10.6mw playback power consumption ? 8khz to 96khz stereo dac with 96db dynamicrange ? 8khz to 48khz stereo adc with 82db dynamicrange ? support for any master clock between 10mhz to60mhz ? stereo microphone inputs support digitalmicrophones ? stereo headphone amplifiers: differential(30mw), single-ended, or capacitorless (10mw) ? stereo line inputs and stereo line outputs ? voiceband filters with stopband attenuationgreater than 70db ? battery-measurement auxiliary adc ? comprehensive headset detection ? dual i 2 s- and tdm-compatible digital audio interfaces ? i 2 c- or spi-compatible control bus with 3.6v tolerant inputs max9880a low-power, high-performance dual i 2 s stereo audio codec ________________________________________________________________ maxim integrated products 1 ordering information 19-5139; rev 1; 3/11 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. evaluation kit available part temp range pin-package max9880aewm+ -40 c to +85 c 48 wlp max9880aetm+ -40 c to +85 c 48 tqfn-ep* functional diagram/typical operating circuit appears at end of data sheet. spi is a trademark of motorola, inc. max9880a mic bias mix left digital filtering right left dac right dac mix mix mix mix mix digital audio interface 1 master clock jack sense/ measurement adc digital audio interface 2 i 2 c interface simplified block diagram downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec 2 __________________________________________________ _____________________________________ absolute maximum ratings electrical characteristics (v avdd = v pvdd = v micvdd = v dvdd = v dvdds1 = +1.8v, r l = , headphone load (r l ) connected between _outp and _outn, dif- ferential modes, c ref = 2.2?, c micbias = c preg = c reg = 1?, av pre = +20db, av pgam = 0db, av dac = 0db, av line = +20db, av vol = 0db, av lo = 0db, f mclk = 13mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 2) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (voltages with respect to agnd.) dvdd, avdd, pvdd ................................................-0.3v to +2v dvdds1, jacksns, micvdd ..............................-0.3v to +3.6v dgnd, pgnd........................................................-0.1v to +0.1v preg, ref, reg ....................................-0.3v to (v avdd + 0.3v) micbias .............................................-0.3v to (v micvdd + 0.3v) mclk, lrclks1, bclks1, sdins1, sdouts1..........................-0.3v to (v dvdds1 + 0.3v) x1, x2, lrclks2, bclks2, sdins2, sdouts2, dout, mode ...................-0.3v to (v dvdd + 0.3v) sda/din, scl/sclk, cs , irq ..............................-0.3v to +3.6v loutp, loutn, routp, routn, loutl, loutr ....................(v pgnd - 0.3v) to (v pvdd + 0.3v) linl, linr, miclp/digmicdata, micln/digmicclk, micrp/spdmdata, micrn/spdmclk ...............................-0.3v to (v avdd + 0.3v) continuous power dissipation (t a = +70 c) 48-bump wlp (derate 12.5mw/ c above +70 c) .....1000mw 48-pin tqfn (derate 37mw/ c above +70 c) ..........2963mw junction temperature ......................................................+150 c operating temperature range ...........................-40 c to +85 c storage temperature range .............................-65 c to +150 c lead temperature (soldering, 10s) .................................+300 c soldering temperature (reflow) .......................................+260 c parameter symbol conditions min typ max units pvdd, dvdd, avdd 1.65 1.8 1.95 supply voltage range dvdds1, micvdd 1.65 1.8 3.6 v analog (avdd + pvdd + micvdd) 5.33 8 full-duplex 8khz mono (note 3) digital (dvdd + dvdds1) 1.4 2 analog (avdd + pvdd + micvdd) 3.5 6 dac playback 48khz stereo (note 3) digital (dvdd + dvdds1) 2.5 4 analog (avdd + pvdd + micvdd) 8.4 12 full-duplex 48khz stereo (note 3) digital (dvdd + dvdds1) 3.0 5 analog (avdd + pvdd + micvdd) 4.9 8 total supply current i vdd stereo line-in to line-out only, t a = +25 c digital (dvdd + dvdds1) 0.012 0.05 ma analog (avdd + pvdd + micvdd) 0.3 2 shutdown supply current t a = +25 c digital (dvdd + dvdds1) 2.6 8 a shutdown to full operation excludes pll lock time 10 ms note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . package thermal characteristics (note 1) tqfn junction-to-ambient thermal resistance ( ja )...............27?/w junction-to-case thermal resistance ( jc )......................1?/w wlp junction-to-ambient thermal resistance ( ja )................42?/w junction-to-case thermal resistance ( jc ).......................5?/w downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec _______________________________________________________________________________________ 3 electrical characteristics (continued)(v avdd = v pvdd = v micvdd = v dvdd = v dvdds1 = +1.8v, r l = , headphone load (r l ) connected between _outp and _outn, dif- ferential modes, c ref = 2.2?, c micbias = c preg = c reg = 1?, av pre = +20db, av pgam = 0db, av dac = 0db, av line = +20db, av vol = 0db, av lo = 0db, f mclk = 13mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 2) parameter symbol conditions min typ max units dac (note 4) master or slave mode 96 dynamic range (note 5) dr f s = 48khz, av vol = 0db, t a = +25 c slave mode 88 db differential mode 1 full-scale output capacitorless and single-ended modes 0.56 v rms gain error dc accuracy, measured with respect to full-scale output 1 5 % f s = 8khz 1.2 voice path phase delay p dly 1khz, 0db input, highpass filter disabled measured from digital input to analog output; mode = 0 (iir voice) f s = 16khz 0.59 ms total harmonic distortion thd f mclk = 12.288mhz, f s = 48khz, 0dbfs, measured at headphone outputs -75 db dac attenuation range av dac vdaca/sdaca = 0xf to 0x0 -15 0 db dac gain adjust av gain vdacg = 00 to 11 0 +18 db v avdd = v pvdd = 1.65v to 1.95v 85 f = 217hz, v ripple = 100mv p-p , av vol = 0db 85 f = 1khz, v ripple = 100mv p-p , av vol = 0db 80 power-supply rejection ratio psrr f = 10khz, v ripple = 100mv p-p , av vol = 0db 74 db dac voice mode digital iir lowpass filter (6x interpolation) with respect to f s within ripple; f s = 8khz to 48khz 0.448 x f s passband cutoff f plp -3db cutoff 0.451 x f s hz passband ripple f < f plp 0.1 db stopband cutoff f slp with respect to f s ; f s = 8khz to 48khz 0.476 x f s hz stopband attenuation f > f slp , f = 20hz to 20khz 75 db dac voice mode digital 5th-order iir highpass filter dvflt = 0x1 (elliptical tuned for 16khz gsm + 217hz notch) 0.0161 x f s dvflt = 0x2 (500hz butterworth tuned for 16khz) 0.0312 x f s dvflt = 0x3 (elliptical tuned for 8khz gsm + 217hz notch) 0.0321 x f s dvflt = 0x4 (500hz butterworth tuned for 8khz) 0.0625 x f s 5th-order passband cutoff (-3db from peak, i 2 c register programmable) f dhppb dvflt = 0x5 (f s /240 butterworth) 0.0042 x f s hz downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec 4 _______________________________________________________________________________________ parameter symbol conditions min typ max units dvflt = 0x1 (elliptical tuned for 16khz gsm + 217hz notch) 0.0139 x f s dvflt = 0x2 (500hz butterworth tuned for 16khz) 0.0156 x f s dvflt = 0x3 (elliptical tuned for 8khz gsm + 217hz notch) 0.0279 x f s dvflt = 0x4 (500hz butterworth tuned for 8khz) 0.0312 x f s 5th-order stopband cutoff (-30db from peak, i 2 c register programmable) f dhpsb dvflt = 0x5 (f s /240 butterworth) 0.0021 x f s hz dc attenuation dc atten dvflt not equal to 000 90 db dac stereo audio mode digital fir lowpass filter (dhf = 0 for f lrclk < 50kh) with respect to f s within ripple; f s = 8khz to 48khz 0.43 x f s -3db cutoff 0.47 x f s passband cutoff f plp -6.02db cutoff 0.50 x f s hz passband ripple f < f plp 0.1 db stopband cutoff f slp with respect to f s ; f s = 8khz to 48khz; f = 0.58 f s to 7.42 f s 0.58 x f s hz stopband attenuation f > f slp 60 db dac stereo audio mode digital fir lowpass filter (dhf = 1 for f lrclk > 50kh) ripple limit cutoff 0.24 x f s passband cutoff f plp -3db cutoff 0.33 x f s hz passband ripple f < f plp 0.1 db stopband cutoff f slp with respect to f s ; f = 0.5 f s to 3.5 f s 0.5 x f s hz stopband attenuation f > f slp 60 db dac stereo audio mode digital dc-blocking highpass filter passband cutoff (-3db from peak) f dhppb dvflt = 0x1 (dai1), dcb = 1 (dai2) 0.000625 x f s hz dc attenuation dc atten dvflt = 0x1 (dai1), dcb = 1 (dai2) 90 db adc (note 6) f s = 8khz, mode = 0 (iir voice), t a = +25 c 72 82 dynamic range (note 5) dr f s = 8khz to 48khz, mode = 1 (fir audio) (note 7) 84 db full-scale input differential mic input or stereo line inputs, av pre = 0db, av pgam = 0db 1 v p-p gain error (note 7) dc accuracy, measured with respect to 80% of full- scale output 1 5 % f s = 8khz 1.2 voice path phase delay 1khz, 0db input, highpass filter disabled measured from analog input to digital output; mode = 0 ( iir voice ) f s = 16khz 0.61 ms electrical characteristics (continued)(v avdd = v pvdd = v micvdd = v dvdd = v dvdds1 = +1.8v, r l = , headphone load (r l ) connected between _outp and _outn, dif- ferential modes, c ref = 2.2?, c micbias = c preg = c reg = 1?, av pre = +20db, av pgam = 0db, av dac = 0db, av line = +20db, av vol = 0db, av lo = 0db, f mclk = 13mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 2) downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec _______________________________________________________________________________________ 5 parameter symbol conditions min typ max units total harmonic distortion thd f = 1khz, f s = 8khz, t a = +25 c, -20db input -80 -70 db adc level adjust av adc avl/avr = 0xf to 0x0 -12 +3 db v avdd = 1.65v to 1.95v, input referred 60 80 f = 217hz, v ripple = 100mv p-p , av adc = 0db, input referred 80 f = 1khz, v ripple = 100mv p-p , av adc = 0db, input referred 78 power-supply rejection ratio psrr f = 10khz, v ripple = 100mv p-p , av adc = 0db, input referred 72 db adc voice mode digital iir lowpass filter with respect to f s within ripple; f s = 8khz to 48khz 0.445 x f s passband cutoff f plp -3db cutoff 0.449 x f s hz passband ripple f < f plp 0.1 db stopband cutoff f slp with respect to f s ; f s = 8khz to 48khz 0.469 x f s hz stopband attenuation f > f slp , f = 20hz to 20khz 74 db adc voice mode digital 5th-order iir highpass filter avflt = 0x1 (elliptical tuned for 16khz gsm + 217hz notch) 0.0161 x f s avflt = 0x2 (500hz butterworth tuned for 16khz) 0.0312 x f s avflt = 0x3 (elliptical tuned for 8khz gsm + 217hz notch) 0.0321 x f s avflt = 0x4 (500hz butterworth tuned for 8khz) 0.0625 x f s passband cutoff (-3db from peak) f ahppb avflt = 0x5 (f s /240 butterworth) 0.0042 x f s hz avflt = 0x1 (elliptical tuned for 16khz gsm + 217hz notch) 0.0139 x f s avflt = 0x2 (500hz butterworth tuned for 16khz) 0.0156 x f s avflt = 0x3 (elliptical tuned for 8khz gsm + 217hz notch) 0.0279 x f s avflt = 0x4 (500hz butterworth tuned for 8khz) 0.0312 x f s stopband cutoff (-30db from peak) f ahpsb avflt = 0x5 (f s /240 butterworth) 0.0021 x f s hz dc attenuation dc atten avflt 000 90 db adc stereo audio mode digital fir lowpass filter with respect to f s within ripple; f s = 8khz to 48khz 0.43 x f s -3db cutoff 0.48 x f s passband cutoff f plp -6.02db cutoff 0.5 x f s hz electrical characteristics (continued)(v avdd = v pvdd = v micvdd = v dvdd = v dvdds1 = +1.8v, r l = , headphone load (r l ) connected between _outp and _outn, dif- ferential modes, c ref = 2.2?, c micbias = c preg = c reg = 1?, av pre = +20db, av pgam = 0db, av dac = 0db, av line = +20db, av vol = 0db, av lo = 0db, f mclk = 13mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 2) downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec 6 _______________________________________________________________________________________ electrical characteristics (continued)(v avdd = v pvdd = v micvdd = v dvdd = v dvdds1 = +1.8v, r l = , headphone load (r l ) connected between _outp and _outn, dif- ferential modes, c ref = 2.2?, c micbias = c preg = c reg = 1?, av pre = +20db, av pgam = 0db, av dac = 0db, av line = +20db, av vol = 0db, av lo = 0db, f mclk = 13mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 2) parameter symbol conditions min typ max units passband ripple f < f plp 0.1 db stopband cutoff f slp with respect to f s ; f s = 8khz to 48khz 0.58 x f s hz stopband attenuation f > f slp , f = 20hz to 20khz 60 db adc stereo audio mode digital dc-blocking highpass filter passband cutoff (-3db from peak) f ahppb avflt = 0x1 0.000625 x f s hz dc attenuation dc atten avflt = 0x1 90 db output volume control voll/volr = 0x00 8.1 8.6 9.2 voll/volr = 0x01 7.6 8.1 8.6 voll/volr = 0x02 7.1 7.6 8.1 voll/volr = 0x04 6.1 6.6 7.2 voll/volr = 0x08 3.1 3.6 4.3 voll/volr = 0x10 -5.9 -5.4 -4.9 voll/volr = 0x20 -60 -55.1 -52 output volume control (note 8) voll/volr = 0x27 -94 -84 -81 db voll/volr = 00x00 to 0x06 (+9db to +6db) 0.5 voll/volr = 00x06 to 0x0f (+6db to +3db) 1 voll/volr = 00x0f to 0x17 (-3db to -19db) 2 output volume control step size voll/volr = 00x17 to 0x27 (-19db to -81db) 4 db output volume control mute attenuation f = 1khz 100 db headphone amplifier (note 9) r l = 16 25 48 output power (differential mode) p out f = 1khz, 0dbfs input, thd < 1%, t a = +25 c r l = 32 30 mw r l = 16 17 output power (capacitorless mode) p out f = 1khz, 0dbfs input, thd < 1%, t a = +25 c r l = 32 10 mw r l = 16 -78 -67 total harmonic distortion + noise (differential mode) thd+n f = 1khz, -3dbfs input r l = 32 -79 db r l = 16 -73 -60 total harmonic distortion + noise (capacitorless mode) thd+n f = 1khz, -3dbfs input r l = 32 -75 db r l = 16 -70 -60 total harmonic distortion + noise (single-ended mode) thd+n f = 1khz, -3dbfs input r l = 32 -70 db dynamic range (notes 5, 7) dr av vol = +6db 77 90 db downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec _______________________________________________________________________________________ 7 electrical characteristics (continued)(v avdd = v pvdd = v micvdd = v dvdd = v dvdds1 = +1.8v, r l = , headphone load (r l ) connected between _outp and _outn, dif- ferential modes, c ref = 2.2?, c micbias = c preg = c reg = 1?, av pre = +20db, av pgam = 0db, av dac = 0db, av line = +20db, av vol = 0db, av lo = 0db, f mclk = 13mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 2) parameter symbol conditions min typ max units v avdd = v pvdd = 1.65v to 1.95v 60 80 f = 217hz, v ripple = 100mv p-p , av vol = 0db 80 f = 1khz, v ripple = 100mv p-p , av vol = 0db 78 power-supply rejection ratio (note 7) psrr f = 10khz, v ripple = 100mv p-p , av vol = 0db 72 db av vol = -81db, differential mode loutp to loutn, routp to routn, t a = +25 c 0.2 output offset voltage v os av vol = -81db, capacitorless mode loutp to loutn, routp to loutn, t a = +25 c 0.6 mv differential, p out = 5mw, f = 1khz 90 crosstalk xtalk capacitorless mode, p out = 5mw, f = 1khz 45 db r l = 32 500 capacitive drive capability no sustained oscillations r l = 100 pf into shutdown -70 click-and-pop level (differential, capacitorless modes) peak voltage, a-weighted, 32 samples per second out of shutdown -70 dbv into shutdown -70 click-and-pop level (single-ended mode) peak voltage, a-weighted, 32 samples per second out of shutdown -70 dbv line outputs (note 7) full-scale output 0.5 v rms logl/logr = 0x00 -0.7 -0.1 +0.6 logl/logr = 0x01 -2.6 -2.1 -1.6 logl/logr = 0x02 -4.6 -4.1 -3.6 logl/logr = 0x04 -8.6 -8.1 -7.6 logl/logr = 0x08 -16.6 -16 -15.6 line output level adjust av lo logl/logr = 0x0f -31.1 -29.9 -29.1 db line output mute attenuation f = 1khz 90 db total harmonic distortion + noise thd+n r l = 1k , f = 1khz, v out = 1.4v p-p (note 9) -67 -59 db 20hz < f < 20khz 86 signal-to-noise ratio r l = 1k , linl/linr = 1f to gnd a-weighted 90 db v avdd = v pvdd = 1.65v to 1.95v 46 f = 217hz, v ripple = 100mv p-p , av vol = 0db 78 f = 1khz, v ripple = 100mv p-p , av vol = 0db 80 power-supply rejection ratio psrr f = 10khz, v ripple = 100mv p-p , av vol = 0db 76 db capacitive drive capability r l = 10k , no sustained oscillations 100 pf downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec 8 _______________________________________________________________________________________ electrical characteristics (continued)(v avdd = v pvdd = v micvdd = v dvdd = v dvdds1 = +1.8v, r l = , headphone load (r l ) connected between _outp and _outn, dif- ferential modes, c ref = 2.2?, c micbias = c preg = c reg = 1?, av pre = +20db, av pgam = 0db, av dac = 0db, av line = +20db, av vol = 0db, av lo = 0db, f mclk = 13mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 2) parameter symbol conditions min typ max units microphone amplifier palen/paren = 01 -0.5 0 +0.5 palen/paren = 10 19.5 20 20.5 preamplifier gain av pre palen/paren = 11 29.3 30 30.5 db pgaml/pgamr = 0x1f -0.5 0 +0.6 mic pga gain av pgam pgaml/pgamr = 0x00 19.3 19.9 20.4 db common-mode rejection ratio cmrr v in = 100mv p-p , f = 217hz 50 db mic input resistance rin_mic all gain settings 30 50 k av pre = 0db v in = 1v p-p , f = 1khz, a-weighted -80 total harmonic distortion + noise thd+n av pre = +30db v in = 32mv p-p , f = 1khz, a-weighted -65 db v avdd = 1.65v to 1.95v, input referred 60 80 f = 217hz, v ripple = 100mv, av adc = 0db, input referred 80 f = 1khz, v ripple = 100mv, av adc = 0db, input referred 78 power-supply rejection ratio psrr f = 10khz, v ripple = 100mv, av adc = 0db, input referred 72 db microphone bias v micvdd = 1.8v, mbias = 0 1.48 1.52 1.56 micbias output voltage v micbias i load = 1ma v micvdd = 3v, mbias = 0 2.15 2.2 2.25 v load regulation i load = 1ma to 2ma, mbias = 0 0.6 10 v/a line regulation v avdd = 1.8v, v micvdd = 1.65v to 1.95v, mbias = 0 1.55 mv/v f = 217hz, v ripple = 100mv p-p 100 power-supply rejection ratio psrr f = 10khz, v ripple = 100mv p-p 90 db noise voltage a-weighted 9.5 v rms line input full-scale input v in av line = 0db 1.0 v p-p ligl/ligr = 0x00 22.8 23.9 24.9 ligl/ligr = 0x01 20.7 21.9 22.9 ligl/ligr = 0x02 18.9 20 20.9 ligl/ligr = 0x04 14.9 16 16.9 line input level adjust av line ligl/ligr = 0x08 6.9 8 8.9 db downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec _______________________________________________________________________________________ 9 electrical characteristics (continued)(v avdd = v pvdd = v micvdd = v dvdd = v dvdds1 = +1.8v, r l = , headphone load (r l ) connected between _outp and _outn, dif- ferential modes, c ref = 2.2?, c micbias = c preg = c reg = 1?, av pre = +20db, av pgam = 0db, av dac = 0db, av line = +20db, av vol = 0db, av lo = 0db, f mclk = 13mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 2) parameter symbol conditions min typ max units line input mute attenuation f = 1khz 100 db input resistance r in_line av line = +24db 20 k total harmonic distortion + noise thd+n v in = 0.1v p-p , f = 1khz -74 db auxin input input dc voltage range auxen = 1 0 0.738 v auxin input resistance r in auxen = 1, 0v v auxin 0.738v 10 40 m jack detect shdn = 1 0.92 x v micbias 0.95 x v micbias 0.98 x v micbias jacksns high threshold v th1 shdn = 0 0.95 x v micvdd d v shdn = 1 0.06 x v micbias 0.10 x v micbias 0.17 x v micbias jacksns low threshold v th2 shdn = 0 0.08 x v micvdd v jacksns sense voltage v sense shdn = 0 v micvdd v jacksns sense resistance r sense shdn = 0 1.9 2.3 3.1 k jacksns deglitch period t glitch 12 300 ms headphone sense threshold 8 1-bit spdm output dynamic range (note 5) dr f s = 48khz, a-weighted, 20hz to 20khz, av vol = 0db; master or slave mode, t a = +25 c 90 db output operational range 0db signal 1s density 25 75 % digital sidetone (mode = 1 iir voice mode only) sidetone gain adjust range av stga differential output mode -60 0 db f s = 8khz 2.2 voice path phase delay p dly mic input to headphone output, f = 1khz, hp filter disabled f s = 16khz 1.1 ms downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec 10 ______________________________________________________________________________________ electrical characteristics (continued)(v avdd = v pvdd = v micvdd = v dvdd = v dvdds1 = +1.8v, r l = , headphone load (r l ) connected between _outp and _outn, dif- ferential modes, c ref = 2.2?, c micbias = c preg = c reg = 1?, av pre = +20db, av pgam = 0db, av dac = 0db, av line = +20db, av vol = 0db, av lo = 0db, f mclk = 13mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 2) parameter symbol conditions min typ max units input clock characteristics mclk input frequency f mclk for any lrclk sample rate 10 60 mhz prescaler = /1 mode 40 60 mclk input duty cycle /2 or /4 modes 30 70 % maximum mclk input jitter maximum allowable rms for performance limits 100 ps dhf = 0 8 48 lrclk sample rate (note 10) dhf = 1 48 96 khz freq1 mode = 0x8 to 0xf 0 0 pclk = 192x, 256x, 384x, 512x, 768x, and 1024x 0 0 lrclk average frequency error (master and slave modes) (note 11) freq1 mode = any clock other than above -0.025 +0.025 % rapid lock mode 2 7 lrclk pll lock time any allowable lrclk and pclk rate, slave mode nonrapid lock mode 12 25 ms lrclk acceptable jitter for maintaining pll lock allowable lrclk period change from nominal for slave pll mode at any allowable lrclk and pclk rates 100 ns soft-start/stop time 10 ms crystal oscillator frequency fundamental mode only 12.288 mhz maximum crystal esr 100 input leakage current i ih , i il x1, t a = +25 c -1 +1 a input capacitance c x1 , c x2 4 pf maximum load capacitor c l1 , c l2 45 pf digital input (mclk) input high voltage v ih 1.2 v input low voltage v il 0.6 v input leakage current i ih , i il t a = +25 c -1 +1 a input capacitance 10 pf digital inputs (sdins1, bclks1, lrclks1) input high voltage v ih 0.7 x v dvdds1 v input low voltage v il 0.3 x v dvdds1 v input hysteresis 200 mv input leakage current i ih , i il t a = +25 c -1 +1 a input capacitance 10 pf downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec ______________________________________________________________________________________ 11 electrical characteristics (continued)(v avdd = v pvdd = v micvdd = v dvdd = v dvdds1 = +1.8v, r l = , headphone load (r l ) connected between _outp and _outn, dif- ferential modes, c ref = 2.2?, c micbias = c preg = c reg = 1?, av pre = +20db, av pgam = 0db, av dac = 0db, av line = +20db, av vol = 0db, av lo = 0db, f mclk = 13mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 2) parameter symbol conditions min typ max units digital inputs (sda, scl, din, sclk, cs , mode, sdins2, bclks2, lrclks2) input high voltage v ih 0.7 x v dvdd v input low voltage v il 0.3 x v dvdd v input hysteresis 200 mv input leakage current i ih , i il t a = +25 c -1 +1 a input capacitance 10 pf digital inputs (digmicdata) input high voltage v ih 0.65 x v dvdd v input low voltage v il 0.35 x v dvdd v input hysteresis 100 mv input leakage current i ih , i il t a = +25 c -35 +35 a input capacitance 10 pf cmos digital outputs (bclks1, lrclks1, sdouts1) output low voltage v ol i ol = 3ma 0.4 v output high voltage v oh i oh = 3ma v dvdds1 - 0.4 v cmos digital outputs (bclks2, lrclks2, sdouts2) output low voltage v ol i ol = 3ma 0.4 v output high voltage v oh i oh = 3ma v dvdd - 0.4 v cmos digital outputs (dout) output low voltage v ol i ol = 1ma, cs = dvdd 0.4 v output high voltage v oh i oh = 1ma, cs = dvdd v dvdd - 0.4 v output low current i ol mode = dvdd, dout = 0, t a = +25 c -1 +1 a output high current i oh mode = dvdd, dout = dvdd, t a = +25 c -1 +1 a cmos digital outputs (digmicclk, spdmdata, spdmclk) output low voltage v ol i ol = 1ma 0.4 v output high voltage v oh i oh = 1ma v dvdd - 0.4 v open-drain digital outputs (sda, irq ) output high current i oh v out = v dvdd , t a = +25 c -1 +1 a output low voltage v ol i ol = 3ma 0.2 x v dvdd v downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec 12 ______________________________________________________________________________________ electrical characteristics (continued)(v avdd = v pvdd = v micvdd = v dvdd = v dvdds1 = +1.8v, r l = , headphone load (r l ) connected between _outp and _outn, dif- ferential modes, c ref = 2.2?, c micbias = c preg = c reg = 1?, av pre = +20db, av pgam = 0db, av dac = 0db, av line = +20db, av vol = 0db, av lo = 0db, f mclk = 13mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 2) parameter symbol conditions min typ max units digital microphone timing characteristics (v dvdd = 1.8v) micclk = 00 1.536 micclk = 01 2.048 digmicclk frequency f micclk f mclk = 12.288mhz micclk = 10 64f s mhz digmicdata to digmicclk setup time t su, mic either clock edge 20 ns digmicdata to digmicclk hold time t hd, mic either clock edge 0 ns spdm timing characteristics spdmclk = 00 1.536 spdmclk = 01 2.048 spdmclk frequency f spdmclk f mclk = 12.288mhz spdmclk = 10 3.072 mhz minimum, f mclk = 20mhz 15 spdmclk to spdmdata delay time t dly,s pdm rising edge spdmclk to right-channel valid spdmdata and falling edge spdmclk to left- channel valid spdmdata maximum, f mclk = 10mhz 65 ns digital audio interface timing characteristics (tdm = 0, v dvdd = 1.8v) bclk cycle time t bclks 75 ns bclk high time t bclkh t a = +25 c 30 ns bclk low time t bclkl t a = +25 c 30 ns bclk or lrclk rise and fall time t r , t f master operation, c l = 15pf 7 ns sdin or lrclk to bclk setup time t su 20 ns sdin or lrclk to bclk hold time t hd 5 ns sdout delay time from bclk rising edge t dly c l = 30pf 0 40 ns digital audio interface timing characteristics (tdm = 1, figure 3, v dvdd = 1.8v) tdm clock frequency 1/t clk tdm mode (tdm = 1) 128 2048 khz tdm clock time high t clkh tdm mode (tdm = 1), t a = +25 c 220 ns tdm clock time low t clkl tdm mode (tdm = 1), t a = +25 c 220 ns short tdm mode (tdm = 1, fsw = 0), master mode (mas = 1) 200 tdm short-sync setup time t syncset short tdm mode (tdm = 1, fsw = 0), slave mode (mas = 0) 20 ns downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec ______________________________________________________________________________________ 13 electrical characteristics (continued)(v avdd = v pvdd = v micvdd = v dvdd = v dvdds1 = +1.8v, r l = , headphone load (r l ) connected between _outp and _outn, dif- ferential modes, c ref = 2.2?, c micbias = c preg = c reg = 1?, av pre = +20db, av pgam = 0db, av dac = 0db, av line = +20db, av vol = 0db, av lo = 0db, f mclk = 13mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 2) parameter symbol conditions min typ max units short tdm mode (tdm = 1, fsw = 0), master mode (mas = 1) 200 tdm short sync hold time t synchold short tdm mode (tdm = 1, fsw = 0), slave mode (mas = 0) 20 ns tdm short sync tx data delay t synctx short tdm mode (tdm = 1, fsw = 0) 12 ns tdm long sync start delay t clksync long tdm mode (tdm = 1, fsw = 1) 3.4 ns tdm long sync end time setup t endsync long tdm mode (tdm = 1, fsw = 1) 51 ns tdm data delay from clock t clktx tdm mode (tdm = 1) 40 ns tdm high-impedance state setup from data t hizout tdm mode (tdm = 1) 120 ns tdm rx data setup time t setup tdm mode (tdm = 1) 20 ns tdm rx data hold time t hold tdm mode (tdm = 1) 20 ns i 2 c timing characteristics (v dvdd = 1.65v) serial-clock frequency f scl 0 400 khz bus free time between stop and start conditions t buf 1.3 s hold time (repeated) start condition t hd,sta 0.6 s scl pulse-width low t low 1.3 s scl pulse-width high t high 0.6 s setup time for a repeated start condition t su,sta 0.6 s data hold time t hd,dat r pu,sda = 475 0 900 ns data setup time t su,dat 100 ns sda and scl receiving rise time t r (note 12) 20 + 0.1c b 300 ns sda and scl receiving fall time t f (note 12) 20 + 0.1c b 300 ns sda transmitting fall time t f r pu,sda = 475 (note 12) 20 + 0.1c b 250 ns setup time for stop condition t su,sto 0.6 s downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec 14 ______________________________________________________________________________________ electrical characteristics (continued)(v avdd = v pvdd = v micvdd = v dvdd = v dvdds1 = +1.8v, r l = , headphone load (r l ) connected between _outp and _outn, dif- ferential modes, c ref = 2.2?, c micbias = c preg = c reg = 1?, av pre = +20db, av pgam = 0db, av dac = 0db, av line = +20db, av vol = 0db, av lo = 0db, f mclk = 13mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 2) parameter symbol conditions min typ max units bus capacitance c b 400 pf pulse width of suppressed spike t sp 0 50 ns spi timing characteristics minimum sclk clock period t cp 40 ns minimum sclk pulse- width low t cl 18 ns minimum sclk pulse- width high t ch 18 ns minimum cs setup time t css 20 ns minimum cs hold time t csh 20 ns minimum cs pulse- width high t csw 20 ns minimum din setup time t ds 5 ns minimum din hold time t dh 5 ns minimum output data propagation dela y t do c l = 50pf 9 ns minimum output data enable time t den 5 ns minimum output data disable time t dz 5 ns note 2: the max9880a is 100% production tested at t a = +25?. specifications over temperature limits are guaranteed by design. note 3: clocking all zeros into the dac. master mode. differential headphone mode. note 4: dac performance measured at headphone outputs. note 5: dynamic range measured using the eiaj method. -60dbfs 1khz output signal, a-weighted, and normalized to 0dbfs. f = 20hz to 20khz. note 6: performance measured using microphone inputs, unless otherwise stated. note 7: performance measured using line inputs. note 8: performance measured using line inputs to line outputs. note 9: performance measured using dac. f mclk = 12.288mhz, f lrclk = 48khz, unless otherwise stated. note 10: lrclk can be any rate in the indicated range. asynchronous or noninteger mclk/lrclk ratios can exhibit some full-scale performance degradation compared to synchronous integer-related mclk/lrclk ratios. note 11: in master-mode operation, the accuracy of the mclk input proportionally determines the accuracy of the sample clockrate. note 12: c b is in pf. downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec ______________________________________________________________________________________ 15 total harmonic distortion + noise vs. power out (dac to headphone) max9880a toc01 power out (mw) thd+n (db) 40 30 20 10 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 05 0 f mclk = 13mhz f lrclk = 8khz r load = 32 differential mode 3khz 1khz 20hz total harmonic distortion + noise vs. power out (dac to headphone) max9880a toc02 power out (mw) thd+n (db) 50 40 30 20 10 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 06 0 f mclk = 13mhz f lrclk = 8khz r load = 16 differential mode 3khz 1khz 20hz total harmonic distortion + noise vs. power out (dac to headphone) max9880a toc03 power out (mw) thd+n (db) 40 30 20 10 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 05 0 f mclk = 12.288mhz f lrclk = 48khz r load = 32 differential mode 6khz 1khz 20hz total harmonic distortion + noise vs. power out (dac to headphone) max9880a toc04 power out (mw) thd+n (db) 50 40 30 20 10 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 06 0 f mclk = 12.288mhz f lrclk = 48khz r load = 16 differential mode 6khz 1khz 20hz total harmonic distortion + noise vs. power out (dac to headphone) max9880a toc05 power out (mw) thd+n (db) 40 30 20 10 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 05 0 f mclk = 12.288mhz f lrclk = 96khz r load = 32 differential mode 6khz 1khz 20hz total harmonic distortion + noise vs. power out (dac to headphone) max9880a toc06 power out (mw) thd+n (db) 50 40 30 20 10 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 06 0 f mclk = 12.288mhz f lrclk = 96khz r load = 16 differential mode 6khz 1khz 20hz total harmonic distortion + noise vs. frequency (dac to headphone) max9880a toc07 frequency (hz) thd+n (db) 1000 100 -85 -80 -75 -70-90 10 10,000 f mclk = 13mhz f lrclk = 8khz r load = 32 differential mode 5mw 20mw total harmonic distortion + noise vs. frequency (dac to headphone) max9880a toc08 frequency (hz) thd+n (db) 1000 100 -88 -86 -84 -82 -80 -78 -76 -74 -72 -70-90 10 10,000 f mclk = 13mhz f lrclk = 8khz r load = 16 ? differential mode 5mw 20mw total harmonic distorton + noise vs. frequency (dac to headphone) max9880a toc09 frequency (hz) thd+n (db) 10k 1k 100 -88 -86 -84 -82 -80 -78 -76 -74 -72 -70-90 10 100k f mclk = 12.288mhz f lrclk = 48khz r load = 32 ? differential mode 5mw 20mw typical operating characteristics (v avdd = v pvdd = v micvdd = v dvdd = v dvdds1 = +1.8v, r l = , headphone load (r l ) connected between _outp and _outn, c ref = 2.2?, c micbias = c preg = c reg = 1?, av pre = +20db, av pgam = 0db, av dac = 0db, av line = +20db, av vol = 0db, av lo = 0db, f mclk = 13mhz, differential output, unless otherwise noted.) downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec 16 ______________________________________________________________________________________ total harmonic distorton + noise vs. frequency (dac to headphone) max9880a toc10 frequency (hz) thd+n (db) 10k 1k 100 -88 -86 -84 -82 -80 -78 -76 -74 -72 -70-90 10 100k f mclk = 12.288mhz f lrclk = 48khz r load = 16 ? differential mode 5mw 20mw total harmonic distorton + noise vs. frequency (dac to headphone) max9880a toc11 frequency (hz) thd+n (db) 10k 1k 100 -88 -86 -84 -82 -80 -78 -76 -74 -72 -70-90 10 100k f mclk = 12.288mhz f lrclk = 96khz r load = 32 ? differential mode 5mw 20mw total harmonic distorton + noise vs. frequency (dac to headphone) max9880a toc12 frequency (hz) thd+n (db) 10k 1k 100 -88 -86 -84 -82 -80 -78 -76 -74 -72 -70-90 10 100k f mclk = 12.288mhz f lrclk = 96khz r load = 16 ? differential mode 5mw 20mw total harmonic distortion + noise vs. power out (dac to headphone) max9880a toc13 power out (mw) thd+n (db) 10 5 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 01 5 f mclk = 13mhz f lrclk = 8khz r load = 32 capacitorless mode 3khz 1khz 20hz total harmonic distortion + noise vs. power out (dac to headphone) max9880a toc14 power out (mw) thd+n (db) 10 5 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 01 5 f mclk = 12.288mhz f lrclk = 48khz r load = 32 capacitorless mode 6khz 1khz 20hz total harmonic distortion + noise vs. power out (dac to headphone) max9880a toc15 power out (mw) thd+n (db) 10 5 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 01 5 f mclk = 12.288mhz f lrclk = 96khz r load = 32 capacitorless mode 1khz 6khz 20hz total harmonic distortion + noise vs. frequency (dac to headphone) max9880a toc16 frequency (hz) thd+n (db) 1000 100 -85 -80 -75 -70 -65 -60-90 10 10,000 f mclk = 13mhz f lrclk = 8khz r load = 32 ? capacitorless mode 1mw 5mw total harmonic distortion + noise vs. frequency (dac to headphone) max9880a toc17 frequency (hz) thd+n (db) 10k 1k 100 -85 -80 -75 -70 -65 -60-90 10 100k f mclk = 12.288mhz f lrclk = 48khz r load = 32 ? capacitorless mode 1mw 5mw total harmonic distortion + noise vs. frequency (dac to headphone) max9880a toc18 frequency (hz) thd+n (db) 10k 1k 100 -85 -80 -75 -70 -65 -60-90 10 100k f mclk = 12.288mhz f lrclk = 96khz r load = 32 ? capacitorless mode 5mw 20mw typical operating characteristics (continued) (v avdd = v pvdd = v micvdd = v dvdd = v dvdds1 = +1.8v, r l = , headphone load (r l ) connected between _outp and _outn, c ref = 2.2?, c micbias = c preg = c reg = 1?, av pre = +20db, av pgam = 0db, av dac = 0db, av line = +20db, av vol = 0db, av lo = 0db, f mclk = 13mhz, differential output, unless otherwise noted.) downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec ______________________________________________________________________________________ 17 total harmonic distortion + noise vs. power out (dac to headphone) max9880a toc19 power out (mw) thd+n (%) 10 8 6 4 2 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40-90 01 2 3khz 1khz 20hz f mclk = 13mhz f lrclk = 8khz r load = 32 single-ended mode total harmonic distortion + noise vs. power out (dac to headphone) max9880a toc20 power out (mw) thd+n (%) 10 8 6 4 2 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40-90 01 2 6khz 1khz 20hz f mclk = 12.288mhz f lrclk = 48khz r load = 32 single-ended mode total harmonic distortion + noise vs. power out (dac to headphone) max9880a toc21 power out (mw) thd+n (db) 12 9 6 3 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 01 5 f mclk = 12.288mhz f lrclk = 96khz r load = 32 single-ended mode 1khz 6khz 20hz total harmonic distortion + noise vs. frequency (dac to headphone) max9880a toc22 frequency (hz) thd+n (db) 1000 100 -85 -80 -75 -70 -65 -60-90 10 10,000 f mclk = 13mhz f lrclk = 8khz r load = 32 ? single-ended mode 1mw 5mw total harmonic distorton + noise vs. frequency (dac to headphone) max9880a toc23 frequency (hz) thd+n (db) 10k 1k 100 -88 -86 -84 -82 -80 -78 -76 -74 -72 -70-90 10 100k 1mw 5mw f mclk = 12.288mhz f lrclk = 48khz r load = 32 ? single-ended mode total harmonic distortion + noise vs. frequency (dac to headphone) max9880a toc24 frequency (hz) thd+n (db) 10k 1k 100 -85 -80 -75 -70 -65 -60-90 10 100k f mclk = 12.288mhz f lrclk = 96khz r load = 32 ? single-ended mode 5mw 20mw total harmonic distortion + noise vs. power out (line-in to headphone) max9880a toc25 power out (mw) thd+n (db) 40 30 20 10 -80 -70 -60 -50 -40 -30 -20 -10 0 -90 05 0 line-in preamp = +18dbr load = 32 differential mode 6khz 1khz 20hz total harmonic distortion + noise vs. power out (line-in to headphone) max9880a toc26 power out (mw) thd+n (db) 40 30 20 10 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 05 0 6khz 1khz 20hz line-in preamp = 0dbr load = 32 differential mode total harmonic distortion + noise vs. frequency (line-in to headphone) max9880a toc27 frequency (hz) thd+n (%) 10,000 1000 100 0.01 0.1 1 10 0.001 10 100,000 line-in preamp = +18dbr load = 32 i differential mode 5mw 20mw typical operating characteristics (continued) (v avdd = v pvdd = v micvdd = v dvdd = v dvdds1 = +1.8v, r l = , headphone load (r l ) connected between _outp and _outn, c ref = 2.2?, c micbias = c preg = c reg = 1?, av pre = +20db, av pgam = 0db, av dac = 0db, av line = +20db, av vol = 0db, av lo = 0db, f mclk = 13mhz, differential output, unless otherwise noted.) downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec 18 ______________________________________________________________________________________ total harmonic distortion + noise vs. frequency (line-in to headphone) max9880a toc28 frequency (hz) thd+n (%) 10,000 1000 100 0.01 0.1 1 10 0.001 10 100,000 line-in preamp = 0dbr load = 32 i differential mode 5mw 20mw total harmonic distortion + noise vs. frequency (dac to line-out) max9880a toc29 frequency (hz) thd+n (db) 1000 100 -80 -70 -60 -50 -40 -30-90 10 10,000 f mclk = 13mhz f lrclk = 8khz 0dbfs fir iir power out vs. headphone load max9880a toc30 headphone load ( ) power out (mw) 100 10 5 10 15 20 25 30 35 40 45 50 0 1 1000 f mclk = 12.288mhz f lrclk = 48khz thd+n 0.1% differential mode output power vs. load resistance (dac to headphone) max9880a toc31 headphone load ( ) power out (mw) 100 10 5 10 15 20 25 0 1 1000 f mclk = 12.288mhz f lrclk = 48khz thd+n 0.1% capacitorless mode power out vs. headphone load max9880a toc32 headphone load ( ) power out (mw) 100 10 5 10 15 20 25 0 1 1000 f mclk = 12.288mhz f lrclk = 48khz thd+n 0.1% single-ended mode total harmonic distortion + noise vs. frequency (microphone to adc) max9880a toc33 frequency (hz) thd+n (%) 1000 100 0.01 0.1 1 10 0.001 10 10,000 f mclk = 13mhz f lrclk = 8khz micpre = 0dbv in = 1v p-p total harmonic distortion + noise vs. frequency (microphone to adc) max9880a toc34 frequency (hz) thd+n (%) 1000 100 0.01 0.1 1 10 0.001 10 10,000 f mclk = 13mhz f lrclk = 8khz micpre = +20dbv in = 100mv p-p total harmonic distortion + noise vs. frequency (microphone to adc) max9880a toc35 frequency (hz) thd+n (%) 1000 100 0.01 0.1 1 10 100 0.001 10 10,000 f mclk = 13mhz f lrclk = 8khz micpre = +30dbv in = 32mv p-p power-supply rejection ratio vs. frequency (dac to headphone) max9880a toc36 frequency (hz) psrr (db) 10k 1k 100 10 -100 -80 -60 -40 -20 0 -120 1 100k f mclk = 12.288mhz f lrclk = 48khz v ripple = 100mv p-p typical operating characteristics (continued) (v avdd = v pvdd = v micvdd = v dvdd = v dvdds1 = +1.8v, r l = , headphone load (r l ) connected between _outp and _outn, c ref = 2.2?, c micbias = c preg = c reg = 1?, av pre = +20db, av pgam = 0db, av dac = 0db, av line = +20db, av vol = 0db, av lo = 0db, f mclk = 13mhz, differential output, unless otherwise noted.) downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec ______________________________________________________________________________________ 19 power-supply rejection ratio vs. frequency (microphone to adc) max9880a toc37 frequency (hz) psrr (db) 10k 1k 100 10 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 1 100k v ripple = 100mv p-p f mclk = 12.288mhz f lrclk = 48khz power-supply rejection ratio vs. frequency (micbias) max9880a toc38 frequency (hz) psrr (db) 10k 1k 100 10 -100 -80 -60 -40 -20 0 -120 1 100k v ripple = 100mv p-p fft, dac to headphone, 0dbfs, f mclk = 13mhz, f lrclk = 8khz max9880a toc39 frequency (hz) amplitude (db) 15k 10k 5k -120 -100 -80 -60 -40 -20 0 20 -140 02 0 k freq1 = 0xa fft, dac to headphone, -60dbfs, f mclk = 13mhz, f lrclk = 8khz max9880a toc40 frequency (hz) amplitude (db) 15k 10k 5k -120 -100 -80 -60 -40 -20 0 20 -140 0 20k freq1 = 0xa fft, dac to headphone, 0dbfs, f mclk = 12.288mhz, f lrclk = 48khz max9880a toc41 frequency (hz) amplitude (db) 15k 10k 5k -120 -100 -80 -60 -40 -20 0 20 -140 0 20k ni = 0x6000 fft, dac to headphone, -60dbfs, f mclk = 12.288mhz, f lrclk = 48khz max9880a toc42 frequency (hz) amplitude (db) 15k 10k 5k -120 -100 -80 -60 -40 -20 0 20 -140 0 20k ni = 0x6000 fft, dac to headphone, 0dbfs, f mclk = 12.288mhz, f lrclk = 96khz max9880a toc43 frequency (hz) amplitude (db) 15k 10k 5k -120 -100 -80 -60 -40 -20 0 20 -140 0 20k ni = 0x6000dhf = 1 fft, dac to headphone, -60dbfs, f mclk = 12.288mhz, f lrclk = 96khz max9880a toc44 frequency (hz) amplitude (db) 15k 10k 5k -120 -100 -80 -60 -40 -20 0 20 -140 0 20k ni = 0x6000dhf = 1 fft, dac to headphone, 0dbfs, f mclk = 13mhz, f lrclk = 48khz max9880a toc45 frequency (hz) amplitude (db) 15k 10k 5k -120 -100 -80 -60 -40 -20 0 20 -140 02 0 k pll mode typical operating characteristics (continued) (v avdd = v pvdd = v micvdd = v dvdd = v dvdds1 = +1.8v, r l = , headphone load (r l ) connected between _outp and _outn, c ref = 2.2?, c micbias = c preg = c reg = 1?, av pre = +20db, av pgam = 0db, av dac = 0db, av line = +20db, av vol = 0db, av lo = 0db, f mclk = 13mhz, differential output, unless otherwise noted.) downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec 20 ______________________________________________________________________________________ fft, dac to headphone, -60dbfs, f mclk = 13mhz, f lrclk = 48khz max9880a toc46 frequency (hz) amplitude (db) 15k 10k 5k -120 -100 -80 -60 -40 -20 0 20 -140 0 20k pll mode fft, dac to headphone, 0dbfs, f mclk = 13mhz, f lrclk = 44.1khz max9880a toc47 frequency (hz) amplitude (db) 15k 10k 5k -120 -100 -80 -60 -40 -20 0 20 -140 0 20k pll mode fft, dac to headphone, -60dbfs, f mclk = 13mhz, f lrclk = 44.1khz max9880a toc48 frequency (hz) amplitude (db) 15k 10k 5k -120 -100 -80 -60 -40 -20 0 20 -140 02 0 k pll mode fft, microphone to adc, 0dbfs, f mclk = 13mhz, f lrclk = 8khz max9880a toc49 frequency (hz) amplitude (db) 3000 2000 1000 -120 -100 -80 -60 -40 -20 0 -140 0 4000 freq1 = 0xa fft, microphone to adc, -60dbfs, f mclk = 13mhz, f lrclk = 8khz max9880a toc50 frequency (hz) amplitude (db) 3000 2000 1000 -120 -100 -80 -60 -40 -20 0 -140 0 4000 freq1 = 0xa fft, microphone to adc, 0dbfs, f mclk = 12.288mhz, f lrclk = 48khz max9880a toc51 frequency (hz) amplitude (db) 15k 10k 5k -120 -100 -80 -60 -40 -20 0 20 -140 02 0 k ni = 0x6000 fft, microphone to adc, -60dbfs, f mclk = 12.288mhz, f lrclk = 48khz max9880a toc52 frequency (hz) amplitude (db) 15k 10k 5k -120 -100 -80 -60 -40 -20 0 20 -140 0 20k ni = 0x6000 fft, microphone to adc, 0dbfs, f mclk = 13mhz, f lrclk = 48khz max9880a toc53 frequency (hz) amplitude (db) 15k 10k 5k -120 -100 -80 -60 -40 -20 0 20 -140 0 20k pll mode fft, microphone to adc, -60dbfs, f mclk = 13mhz, f lrclk = 48khz max9880a toc54 frequency (hz) amplitude (db) 15k 10k 5k -120 -100 -80 -60 -40 -20 0 -140 0 20k pll mode typical operating characteristics (continued) (v avdd = v pvdd = v micvdd = v dvdd = v dvdds1 = +1.8v, r l = , headphone load (r l ) connected between _outp and _outn, c ref = 2.2?, c micbias = c preg = c reg = 1?, av pre = +20db, av pgam = 0db, av dac = 0db, av line = +20db, av vol = 0db, av lo = 0db, f mclk = 13mhz, differential output, unless otherwise noted.) downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec ______________________________________________________________________________________ 21 wideband fft, dac to headphone, 0dbfs, f mclk = 13mhz, f lrclk = 8khz max9880a toc55 frequency (hz) amplitude (db) 100k 80k 20k 40k 60k -120 -100 -80 -60 -40 -20 0 20 -140 0 120k freq1 = 0xa wideband fft, dac to headphone, -60dbfs, f mclk = 13mhz, f lrclk = 8khz max9880a toc56 frequency (hz) amplitude (db) 100k 80k 60k 40k 20k -120 -100 -80 -60 -40 -20 0 -140 0 120k freq1 = 0xa dac iir highpass filter frequency response, mode = 0 max9880a toc57 frequency (hz) amplitude (db) 500 400 300 200 100 -80 -60 -40 -20 0 20 -100 0 600 f lrclk = 8khz dvflt = 0 dvflt = 3 dvflt = 4 adc iir highpass filter frequency response, mode = 0 max9880a toc58 frequency (hz) amplitude (db) 500 400 300 200 100 -80 -60 -40 -20 0 20 -100 0 600 f lrclk = 8khz avflt = 0 avflt = 3 avflt = 4 dac iir/fir lowpass filter frequency response (f lrclk = 8khz) max9880a toc59 frequency (hz) amplitude (db) 3800 3600 3400 3200 -80 -60 -40 -20 0 20 -100 3000 4000 mode = 1 mode = 0 dac fir lowpass filter frequency response (f lrclk = 96khz) max9880a toc60 frequency (hz) amplitude (db) 44k 40k 36k 32k 28k 24k -80 -60 -40 -20 0 20 -100 20k 48k adc iir/fir lowpass filter frequency response (f lrclk = 8khz) max9880a toc61 frequency (hz) amplitude (db) 3800 3600 3400 3200 -80 -60 -40 -20 0 20 -100 3000 4000 mode = 1 mode = 0 shutdown to full operation (differential) max9880a toc62 time (4ms/div) scl (1v/div) loutp (500mv/div) shutdown to full operation (se clickless) max9880a toc63 time (40ms/div) scl (1v/div) loutp (500mv/div) typical operating characteristics (continued) (v avdd = v pvdd = v micvdd = v dvdd = v dvdds1 = +1.8v, r l = , headphone load (r l ) connected between _outp and _outn, c ref = 2.2?, c micbias = c preg = c reg = 1?, av pre = +20db, av pgam = 0db, av dac = 0db, av line = +20db, av vol = 0db, av lo = 0db, f mclk = 13mhz, differential output, unless otherwise noted.) downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec 22 ______________________________________________________________________________________ shutdown to full operation (se fast turn on) max9880a toc64 time (4ms/div) scl (1v/div) loutp (500mv/div) full operation to shutdown max9880a toc65 time (400 s/div) scl (1v/div) loutp (500mv/div) soft-start adc max9880a toc66 time (1ms/div) scl (1v/div) adc output (500mv/div) total harmonic distortion + noise vs. mclk frequency, 0dbfs max9880a toc67 mclk frequency (mhz) thd+n (db) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 10 100 f lrclk = 48khz pll mode dynamic range vs. mclk frequency max9880a toc68 mclk frequency (mhz) dynamic range (db) 70 80 90 100 110 120 60 10 100 v in = -60dbfs f lrclk = 48khz pll mode line input resistance vs. gain setting max9880a toc69 gain setting (db) input resistance (k ) 20 15 10 5 0 -5 50 100 150 200 250 300 0 -10 25 aux code vs. input voltage max9880a toc70 input voltage (v) aux code (signed decimal) 1.0 0.8 0.6 0.4 0.2 0 -0.2 0 5000 10,000 15,000 20,000 25,000 30,000 -5000 -0.4 1.2 typical operating characteristics (continued) (v avdd = v pvdd = v micvdd = v dvdd = v dvdds1 = +1.8v, r l = , headphone load (r l ) connected between _outp and _outn, c ref = 2.2?, c micbias = c preg = c reg = 1?, av pre = +20db, av pgam = 0db, av dac = 0db, av line = +20db, av vol = 0db, av lo = 0db, f mclk = 13mhz, differential output, unless otherwise noted.) downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec ______________________________________________________________________________________ 23 pin configurations top view (bump side down) 1 ab cd 234 wlp ef 5678 irq x2 x1 dgnd agnd preg avdd mode cs scl/sclk sda/din dvdd micbias micvdd ref dout n.c. bclks2 lrclks2 sdins2 micrp/ spdmdata micln/ digmicclk reg n.c. n.c. sdins1 sdouts2 mclk micrn/ spdmclk miclp/ digmicdata n.c. jacksns/ aux loutp pvdd bclks1 lrclks1 linl loutl pgnd routp loutn pvdd dvdds1 sdouts1 linr loutr pgnd routn max9880a + top view thin qfn (6mm 6mm) 13 14 15 16 17 18 19 20 21 22 23 24 reg n.c. agnd micvdd micbias micln/digmicclk miclp/digmicdata micrp/spdmdata micrn/spdmclk jacksns/aux linl linr 48 47 46 45 44 43 42 41 40 39 38 37 1 2 34 5 678910 11 12 n.c. dgnd dvdd bclks2 lrclks2 sdins2 sdouts2 mclk bclks1 lrclks1 sdins1 sdouts1 preg n.c. ref avdd irq mode dout cs x2 x1 scl/sclk sda/din 36 35 34 33 32 31 30 29 28 27 26 25 loutr loutl pgnd n.c. routp routn loutn loutp n.c. pvdd n.c. dvdds1 + max9880a *ep *ep = exposed pad downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec 24 ______________________________________________________________________________________ pin description pin tqfn-ep wl p name function 1 b2 sda/din i 2 c serial-data input/output (mode = 0). connect a pullup resistor to dvdd for full output swing. spi compatible serial-data input (mode = 1). 2 b3 scl/sclk i 2 c serial-clock input (mode = 0). connect a pullup resistor to dvdd for full output swing. spi-compatible serial clock input (mode = 1). 3 a2 x1 crystal oscillator input. connect load capacitor and one terminal of the cr ystal to this pin. acceptable input frequency range: 10mhz to 30mhz. 4 a3 x2 crystal oscillator output. connect load capacitor and second termin al of the crystal to this pin. 5 b4 cs spi-compatible, active-low chip-select input 6 b5 dout spi-compatible serial-data output 7 a5 mode i 2 c/spi mode select input (mode = 0 for i 2 c mode, mode = 1 for spi mode) 8 a4 irq hardware interrupt output. irq can be programmed to go low when bits in the status register 0x00 are set. read status register 0x00 to clear irq once set. repeat faults have no effect on irq until it is cleared by reading the i 2 c status register 0x00. connect a 10k pullup resistor to dvdd for full output swing. 9 a6 avdd analog power supply. bypass to agnd with a 1f capacitor. 10 b6 ref converter reference. bypass to agnd with a 2.2f capacitor (1.23v nominal). 11, 14, 28, 33, 35, 48 c4, d4, c5, d6 n.c. no connection. connect to gnd. 12 a7 preg positive internal regulated supply. bypass to agnd with a 1f capacito r (1.6v nominal). 13 c6 reg preg/2 voltage reference. bypass to agnd with a 1f capacitor (0.8v nominal) 15 a8 agnd analog ground 16 b7 micvdd microphone bias power supply. bypass to agnd with a 1 f capacitor. 17 b8 micbias low-noise microphone bias. connect a 2.2k to 470 resistor to the positive output of the microphone. bypass to agnd with a 1f capacitor. 18 c7 micln/ digmicclk left negative differential microphone input. ac-couple a microphone with a series 1f capacitor. also digital microphone clock output. selectable through i 2 c. 19 d7 miclp/ digmicdata left positive differential microphone input. ac-couple a microphone with a series 1f capacitor. also digital microphone data input. selectable th rough i 2 c. 20 c8 micrp/ spdmdata right positive differential microphone input or spdm data output. ac-couple a microphone with a series 1f capacitor. selectable through i 2 c. 21 d8 micrn/ spdmclk right negative differential microphone input or spdm clock output. ac-c ouple a microphone with a series 1f capacitor. selectable through i 2 c. 22 d5 jacksns/aux jack sense. detects the presence or absence of a jack. see the headset detection section. when used as an auxiliary adc input, aux is used to measure dc voltages. downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec ______________________________________________________________________________________ 25 pin description (continued) pin tqfn-ep wl p name function 23 e8 linl left-line input. ac-couple analog audio signal to linl with a 1f capacitor. 24 f8 linr right-line input. ac-couple analog audio signal to linr with a 1f ca pacitor. 25 f7 loutr right-line output 26 e7 loutl left-line output 27 e6, f6 pgnd headphone power ground 29 e5 routp positive right-channel headphone output. connect directly to the load in differential and capacitorless mode. ac-couple to the load in single-ended mode. 30 f5 routn negative right-channel headphone output. unused in capacitorless and single-ended mode. 31 f4 loutn negative left-channel headp hone output. common headphone return in capacitorless mode. unused in single-ended mode. 32 e4 loutp positive left-channel headphone output. connect directly to the load in differential and capacitorless mode. ac-couple to the load in single-ended mode. 34 e3, f3 pvdd headphone power supply. bypass to pgnd with a 1f capac itor. 36 f2 dvdds1 s1 digital audio interface power-supply input. bypass to dgnd wi th a 1f capacitor. 37 f1 sdouts1 s1 digital audio serial-data adc output 38 d3 sdins1 s1 digital audio serial-data dac input 39 e1 lrclks1 s1 digital audio left-right clock input/output. lrclks1 is the audio sample rate clock and determines whether the audio data on sdins1 is routed to the left or right channel. in tdm mode, lrclks1 is a frame sync pulse. lrclks1 is an input when the max9880a is in slave mode and an output when in master mode. 40 e2 bclks1 s1 digital audio bit clock input/output. bclks1 is an input when the max9880a is in slave mode and an output when in master mode. 41 d1 mclk master clock input. acceptable input frequency range: 10mhz to 60mhz. 42 d2 sdouts2 s2 digital audio serial-data adc output 43 c1 sdins2 s2 digital audio serial-data dac input 44 c2 lrclks2 s2 digital audio left-right clock input/output. lrclks2 is the audio sample rate clock and determines whether the audio data on sdins2 is routed to the left or right channel. in tdm mode, lrclks2 is a frame sync pulse. lrclks2 is an input when the max9880a is in slave mode and an output when in master mode. 45 c3 bclks2 s2 digital audio bit clock input/output. bclks2 is an input when the max9880a is in slave mode and an output when in master mode. 46 b1 dvdd digital power supply. supply for the digital core and i 2 c/spi interface. bypass to dgnd with a 1.0f capacitor. 47 a1 dgnd digital ground ep exposed pad. connect the exposed thermal pad to agnd. downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec 26 ______________________________________________________________________________________ detailed description the max9880a is a low-power stereo audio codecdesigned for portable applications requiring minimum power consumption. the stereo playback path accepts digital audio through flexible digital audio interfaces compatible with i 2 s, tdm, and left-justified audio signals. the max9880acan process two simultaneous digital input streams that can be mixed digitally. the primary interface is intend- ed for voiceband applications, while the secondary interface can be used for stereo audio data. an over- sampling sigma-delta dac converts the mixed incom- ing digital data stream to analog audio and outputs through the stereo headphone amplifier and stereo-line outputs. the headphone amplifier can be configured in differential, single-ended, and capacitorless output modes. the stereo record path has two differential analog microphone inputs with selectable gain. the micro- phones are powered by an integrated microphone bias. the max9880a can retask the left analog microphone input to accept data from up to two digital micro- phones. an oversampling sigma-delta adc converts the microphone signals and outputs the digital bit stream over the digital audio interface. an auxiliary adc allows accurate measurements of dc voltages by retasking the right audio adc. dc voltages can be read through the registers. the max9880a also includes two line inputs. these inputs allow a stereo single-ended signal to be gain adjusted and then recorded by the adcs and output by the headphone amplifier and line output amplifiers. a jack detection function allows the detection of head- phone, microphone, and headset jacks. insertion and removal events can be programmed to trigger a hard- ware interrupt and flag a register bit. the max9880a? flexible clock circuitry utilizes a pro-grammable clock divider and a digital pll to allow the dac and adc to operate at maximum dynamic range for all combinations of master clock (mclk) and sam- ple rate (lrclk) without consuming extra supply cur- rent. any master clock between 10mhz and 60mhz is supported as are all sample rates from 8khz to 48khz for the record path and 8khz to 96khz for the playback path. master and slave modes are supported for maxi- mum flexibility. the right analog microphone input can be retasked to output spdm data. integrated digital filtering provides a range of notch and highpass filters for both the play- back and record paths to limit undesirable low-frequen- cy signals and gsm transmission noise. the digital filtering provides attenuation of out-of-band energy by over 70db, eliminating audible aliasing. a digital sidetone function allows audio from the record path to be summed into the playback path after digital filtering. i 2 c/spi registers forty internal registers program and report the status ofthe max9880a. table 1 lists all of the registers, their addresses, and power-on-reset states. registers 0x00?x03 are read-only while all of the other registers are read/write. write zeros to all unused bits in the regis- ter table when updating the register, unless otherwise noted. all bits in the read-only registers are not pro- grammable. read operations of unused bits return zero. i 2 c slave address the max9880a is preprogrammed with a slaveaddress of 0x20 or 0010000. the address is defined as the 7 most significant bits (msbs) followed by the read/write bit. set the read/write bit to 1 to configure the max9880a to read mode. set the read/write bit to zero to configure the max9880a to write mode. the address is the first byte of information sent to the max9880a after the start (s) condition. register b7 b6 b5 b4 b3 b2 b1 b0 register address (see note) por state r/w status status cld sld ulk * * jdet 0x00 r jack status jksns[1:0] 0x01 r aux high aux[15:8] 0x02 r aux low aux[7:0] 0x03 r interrupt enable icld isld iulk 0 0* 0* ijdet 0 0x04 0x00 r/w system clock control system clock 0 0 psclk freq1 0x05 0x00 r/w table 1. register map downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec ______________________________________________________________________________________ 27 register b7 b6 b5 b4 b3 b2 b1 b0 register address (see note) por state r/w dai1 clock control stereo audio clock control high pll1 ni1[14:8] 0x06 0x00 r/w stereo audio clock control low ni1[7:1] rlk1/ni1[0] 0x07 0x00 r/ w dai1 configuration int erfac e m ode a m as1 wci1 bci 1 dly1 hizoff1 tdm 1 fsw1 0 0x08 0x00 r/w interface mode b dl1 sel1 sdoen1 sdien1 dmono1 bsel1 0x09 0x00 r /w time-division multiplex slotl1 slotr1 slotdly1[3:0] 0x0a 0x00 r /w dai2 clock control stereo audio clock control high pll2 ni2[14:8] 0x0b 0x00 r/w stereo audio clock control low ni2[7:1] rlk2/ni2[0] 0x0c 0x00 r /w dai2 configuration int erfac e m ode a m as2 wci2 bci 2 dly2 hizoff2 tdm 2 fsw2 w s2 0 x0 d 0 x0 0 r/w interface mode b dl2 sel2 sdoen2 sdien2 dhf bsel2 0x0e 0x00 r/w time-division multiplex slotl2 slotr2 slotdly2[3:0] 0x0f 0x00 r /w digital mixers dac-l/r mixer mixdal mixdar 0x10 0x00 r/w digital filtering codec filters mode avflt dcb dvflt 0x11 0x00 r/w spdm outputs configuration spdmclk spdml spdmr 0 0 0 0 0x12 0x00 r/w input mixspdml mixspdmr 0x13 0x00 r/w revision id rev id location (replicated for spi mode) rev 0x14 0x42 r/w level control sidetone dsts 0 dvst 0x15 0x00 r/w stereo dac level 0 sdacm 0 0 sdaca 0x16 0x00 r/w voice dac level 0 vdacm vdacg vdaca 0x17 0x00 r/w left adc level 0 0 avlg avl 0x18 0x00 r/w right adc level 0 0 avrg avr 0x19 0x00 r/w left-line input level 0 lilm 0 0 ligl 0x1a 0x00 r/w right-line input level 0 lirm 0 0 ligr 0x1b 0x00 r/w left volume control 0 vollm voll 0x1c 0x00 r/w right volume control 0 volrm volr 0x1d 0x00 r/w left-line output level 0 lolm 0 0 logl 0x1e 0x00 r/w right-line output level 0 lorm 0 0 logr 0x1f 0x00 r/w left microphone gain 0 palen pgaml 0x20 0x00 r/w right microphone gain 0 paren pgamr 0x21 0x00 r/w configuration input mxinl mxin r auxcap auxgain auxcal a uxen 0 x2 2 0 x0 0 r /w microphone micclk digmicl digmicr 0 0 0 mbias 0x23 0x00 r/w mode dslew vsen zden 0 0 hpmode 0x24 0x00 r/w jack detect jdeten 0 jdwk 0 0 0 jdeb 0x25 0x00 r/w table 1. register map (continued) downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec 28 ______________________________________________________________________________________ device status status registers 0x00 and 0x01 are read-only registersthat report the status of various device functions. the status register bits are cleared upon reading the status register and are set the next time the event occurs. registers 0x02 and 0x03 report the dc level applied to aux. see the adc section for more details. bits in status register 0x00 are set when an alert condi-tion exists. all bits in status register 0x00 are automati- cally cleared upon a read operation of the register and are set again if the condition remains or occurs follow- ing the read of this register. register b7 b6 b5 b4 b3 b2 b1 b0 register address (see note) por state r/w power management enable lnlen lnren lolen loren dalen daren adlen adren 0x26 0x0 0 r/w system shutdown shdn 0 0 0 xten xtosc 0 0 0x27 0x00 r/w revision id revision id rev 0xff 0x42 r/w table 1. register map (continued) * reserved. grayed boxes = not used. note: register addresses listed are for i 2 c. to get the spi address, add 0x200 with the following exception: register 0xff is not accessible through spi. register b7 b6 b5 b4 b3 b2 b1 b0 register address (see note) status cld sld ulk * * jdet 0x00 jack status jksns[1:0] 0x01 aux high aux[15:8] 0x02 aux low aux[7:0] 0x03 table 2. status register * reserved. grayed boxes = not used. note: register addresses listed are for i 2 c. to get the spi address, add 0x200 with the following exception: register 0xff is not accessible through spi. downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec ______________________________________________________________________________________ 29 bits function cld clip detect flag . indicates that a signal has become clipped in the adc or dac. to re solve a clip condition in the signal path, the dac gain settings and analog input gain setting s should be lowered. as the cld bit does not indicate where the overload has occurred, identify the source by low ering gains individually. sld slew level detect flag . when volume or gain changes are made, the slewing circuitry smoothly s teps through all intermediate settings. when sld is set high, all slewing ha s completed and the volume or gain is at its final value. sld is also set when soft start or stop is complete. ulk digital pll unlock flag . indicates that the digital audio pll has become unlocked and digital si gnal data is not reliable. jdet headset configuration change flag. jdet reports changes in jksns[1:0]. changes to jksns[1:0] are debounced before setting jdet. the debounce period is programmable using the j deb bits. jksns reports the status of the jacksns pin when jdeten = 1. jksns is not debounced and should be interpreted according to the following information. jksns[1:0] description 00 jacksns is below v th2 . 01 jacksns is between v th1 and v th2 . 10 invalid. jksns[1:0] 11 jacksns is above v th1 . aux auxiliary input measurement. aux is a 16-bit signed twos complement number representing the volt age measured at jacksns/aux. before reading a value from aux, set aux cap to 1 to ensure a stable reading. after reading the value, set auxcap to 0. use the following formula to convert the aux value into an equivalent jack sns/aux voltage: voltage = 0.738v aux k k = aux value when auxgain = 1. see auxgain for details on determin ing the value of k, the calibration constant. table 3. status register bits downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec 30 ______________________________________________________________________________________ hardware interrupts hardware interrupts are reported on the open-drain irq pin. when an interrupt occurs, irq remains low until the interrupt is serviced by reading the status register 0x00. if a flag is set, it is reported as a hardware interrupt onlyif the corresponding interrupt enable is set. each bit enables interrupts for the status flag in the respective bit location in register 0x00. register b7 b6 b5 b4 b3 b2 b1 b0 register address (see note) interrupt enable icld isld iulk 0 0* 0* ijdet 0 0x04 table 4. interrupt enable * reserved. grayed boxes = not used. note: register addresses listed are for i 2 c. to get the spi address, add 0x200 with the following exception: register 0xff is not accessible through spi. register b7 b6 b5 b4 b3 b2 b1 b0 register address (see note) system clock control system clock 0 0 psclk freq1 0x05 dai1 clock control stereo audio clock control high pll1 ni1[14:8] 0x06 stereo audio clock control low ni1[7:1] rlk1/ni1[0] 0x07 dai2 clock control stereo audio clock control high pll2 ni2[14:8] 0x0b stereo audio clock control low ni2[7:1] rlk2/ni2[0] 0x0c table 5. system and audio clock registers grayed boxes = not used. note: register addresses listed are for i 2 c. to get the spi address, add 0x200 with the following exception: register 0xff is not accessible through spi. clock control the max9880a can work with a master clock (mclk)supplied from any system clock within the 10mhz to 60mhz range. internally the max9880a requires a 10mhz to 20mhz clock. a prescaler divides mclk by 1, 2, or 4 to create the internal clock (pclk). pclk is used to clock all portions of the max9880a. the max9880a can support any sample rate from 8khz to 48khz for the digital audio path dai1 (dac and adc) and 8khz to 96khz for the dai2 (high-fidelity dac path), including all common sample rates (8khz, 16khz, 24khz, 32khz, 44.1khz, 48khz, 96khz). to accommodate a wide range of system architectures, the max9880a supports three main clocking modes: normal mode: this mode uses a 15-bit clock divider coefficient to set the sample rate relative tothe prescaled mclk input (pclk). this allows high flexibility in both the mclk and lrclk frequenciesand can be used in either master or slave mode. exact integer mode: common mclk frequencies (12mhz, 13mhz, 16mhz, and 19.2mhz) can be pro-grammed to operate in exact integer mode for both 8khz and 16khz sample rates. in these modes, the mclk and lrclk rates are selected by using the freq1 bits instead of the ni high, ni low, and pll con- trol bits. pll mode: when operating in slave mode, a pll can be enabled to lock onto externally generatedlrclk signals that are not integer related to pclk. prior to enabling the interface, program ni to the nearest desired ratio and set the ni[0] = 1 to enable the pll? rapid lock mode. if ni[0] = 0, then ni is ignored and pll lock time is slower. downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec ______________________________________________________________________________________ 31 bits function psclk mclk prescaler. divides mclk down to generate a pclk between 10mhz and 20mhz. 00 = disable clock for low-power shutdown. 01 = select if mclk is between 10mhz and 20mhz. pclk = mclk. 10 = select if mclk is between 20mhz and 40mhz. pclk = mclk/2. 11 = select if mclk is greater than 40mhz. pclk = mclk/4. exact integer modes. allows integer sampling for specific pclk (prescaled mclk) freq uencies and 8khz or 16khz sample rates. freq1[3:0] pclk (mh) lrclk (kh) pclk/lrclk 0x00 normal or pll mode 0x1C0x7 reserved reserved reserved 0x8 0x9 1212 8 16 1500 750 0xa 0xb 1313 8 16 1625 812.5 0xc 0xd 1616 8 16 2000 1000 0xe 0xf 19.2 19.2 8 16 2400 1200 freq1 modes 0x8 to 0xf are available in either master or slave mode. in slav e mode, if the indicated pclk/lrclk ratio cannot be guaranteed, use pll mode instead. pll1/pll2 pll mode enable 0 = (valid for slave and master mode) the frequency of lrclk is set by the ni divider bits. in master mode, the max9880a generates lrclk using the specified divide ratio. in s lave mode, the max9880a expects an lrclk as specified by the divide ratio. 1 = (valid for slave mode only) a digital pll locks on to any externally su pplied lrclk signal. rlk1/rlk2 rapid lock mode. to enable rapid lock mode set ni_ to the nearest desired ratio and s et rlk_ = 1 before enabling the interface. ni1/ni2 normal mode lrclk divider. when pll = 0, the frequency of lrclk is determined by ni. see table 6 for common ni values. for lrclk = 8khz to 48khz operation (dhf = 0 for dai2): ni = (65,536 x 96 x f lrclk )/f pclk f lrclk = lrclk frequency f pclk = prescaled internal mclk frequency (pclk) for lrclk > 50khz operation (dhf = 1 for dai2): ni = (65,536 x 48 x f lrclk )/f pclk f lrclk = lrclk frequency f pclk = prescaled internal mclk frequency (pclk) table 5. system and audio clock registers (continued) downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec 32 ______________________________________________________________________________________ digital audio interface the max9880a? dual digital audio interface supports awide range of operating modes to ensure maximum compatibility. see figures 1 to 5 for timing diagrams. in master mode, the max9880a outputs lrclk and bclk, while in slave mode they are inputs. when oper- ating in master mode, bclk can be configured in a number of ways to ensure compatiblity with other audio devices. the max9880a has two sets of digital audio interface pins, s1 and s2, that can be connected to one of two digital audio paths, dai1 or dai2. dai1: digital audio path 1 operation dac path with dr of 90db and adc path with dr of 82db dac path connectable to either s1 or s2 adc path connectable to either s1 or s2 8khz to 48khz sample rates ? 2 s and tdm-compatible modes voice filters or audio filter modes dai2: digital audio path 2 operation high-fidelity dac path with dr of 96db dac path connectable to either s1 or s2 8khz to 96khz sample rates ? 2 s and tdm-compatible modes audio fir filters no adc clock control from dai2 sample clock and no voice filter modes available in dai2 (dai1, dai2 for dhf = 0) (dai2 for dhf = 1) lrclk (kh) 8 11.025 12 16 22.05 24 32 44.1 48 64 88.2 96 10 13a9 1b18 1d7e 2752 3631 3afb 4ea5 6c61 75f7 4ea5 6c61 75f7 11 11e0 18a2 1acf 23bf 3144 359f 477e 6287 6b3e 477e 6287 6b3e 11.2896 116a 1800 1a1f 22d4 3000 343f 45a9 6000 687d 45a9 6000 687d 12 1062 1694 1893 20c5 2d29 3127 4189 5a51 624e 4189 5a51 624e 12.288 1000 160d 1800 2000 2c1a 3000 4000 5833 6000 4000 5833 6000 13 f20 14d8 16af 1e3f 29af 2d5f 3c7f 535f 5abe 3c7f 535f 5abe 14 e0b 135b 1511 1c16 26b5 2a21 382c 4d6a 5443 382c 4d6a 5443 15 d1b 1210 13a9 1a37 2420 2752 346e 4841 4ea5 346e 4841 4ea5 16 c4a 10ef 126f 1893 21de 24dd 3127 43bd 49ba 3127 43bd 49ba 16.9344 b9c 1000 116a 1738 2000 22d4 2e71 4000 45a9 2e71 4000 45a9 17 b91 ff0 1159 1721 1fe0 22b2 2e43 3fc1 4564 2e43 3fc1 4564 18 aec f0e 1062 15d8 1e1b 20c5 2bb1 3c36 4189 2bb1 3c36 4189 18.432 aab eb3 1000 1555 1d66 2000 2aab 3acd 4000 2aab 3acd 4000 19 a59 e43 f86 14b2 1c85 1f0b 2964 390b 3e16 2964 390b 3e16 pclk (mh): (note: any pclk from 10mhz to 20mhz with any lrclk 7.8khz to 50khz can be used.) 20 9d5 d8c ebf 13a9 1b18 1d7e 2752 3631 3afb 2752 3631 3afb table 6. common ni values note: values in bold and underline are exact integers that provide maximum full-scale performance. downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec ______________________________________________________________________________________ 33 register b7 b6 b5 b4 b3 b2 b1 b0 register address (see note) dai1 configuration interface mode a mas1 wci1 bci1 dly1 hizoff1 tdm1 fsw1 0 0x08 interface mode b dl1 sel1 sdoen1 sdien1 dmono1 bsel1 0x09 time-division multiplex slotl1 slotr1 slotdly1[3:0] 0x0a dai2 configuration interface mode a mas2 wci2 bci2 dly2 hizoff2 tdm2 fsw2 ws2 0x0d interface mode b dl2 sel2 sdoen2 sdien2 dhf bsel2 0x0e time-division multiplex slotl2 slotr2 slotdly2[3:0] 0x0f bits function mas1/2 master mode 0 = the max9880a operates in slave mode with lrclk and bclk configured as i nputs. 1 = the max9880a operates in master mode with lrclk and bclk configured as outputs. wci1/2 lrclk invert (tdm1/2 = 0) 0 = left-channel data is input and output while lrclk is low. 1 = right-channel data is input and output while lrclk is low. bci1/2 bclk invert in master and slave modes: 0 = sdin is latched into the part on the rising edge of bclk. sdout tr ansitions immediately after the rising edge of bclk. 1 = sdin is latched into the part on the falling edge of bclk. s dout transitions immediately after the falling edge of bclk. in master mode: 0 = lrclk changes state immediately after the rising edge of bclk. 1 = lrclk changes state immediately after the falling edge of bclk. dly1/2 delay mode. dly1/2 have two different functions in tdm and non-tdm mode. in non-tdm mode (tdm1/tdm2 = 0): the functionality is as follows: 1 = the most significant bit of an audio word is latched at the secon d bclk edge after the lrclk transition. 0 = the most significant bit of an audio word is latched at the first bclk edge after the lrclk transition. in tdm mode (tdm1/tdm2 = 1): the functionality is as follows: 1 = the hold time on the sdout output is increased to be greater than 150ns. 0 = the hold time on the sdout output is the default (greater than 20n s but less than 150ns). hizoff1/2 sdout high-impedance mode 0 = sdout goes to a high-impedance state after all data bits have been transferred out of the max9880a, allowing sdout to be shared by other devices. 1 = sdout is set either high or low after all data bits have bee n transferred out of the max9880a. note: high-impedance mode is intended for use when tdm = 1. table 7. digital audio interface registers grayed boxes = not used. note: register addresses listed are for i 2 c. to get the spi address, add 0x200 with the following exception: register 0xff is not accessible through spi. downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec 34 ______________________________________________________________________________________ bits function tdm1/2 tdm mode select 1 = enables time-division multiplex mode and configures the audi o interface to accept pcm data. 0 = disables time-division multiplex mode. lrclk signal polarity in dicates left and right audio. fsw1/2 frame sync width 1 = frame sync pulse extended to the width of the entire 16-bit first s lot 0 data word (tdm1/tdm2 = 1 only; slotdly[0] must be 0 when fsw is set to 1). 0 = frame sync pulse is 1 bit wide. ws2 word sie 0 = the number of bits per input data word sample is 16 bits, and at least 16 bclks per input word are required. 1 = the number of bits per input data word sample is 18 bits, and at least 18 bclks per input word transfer is required. these control bits are only recognized when tdm1/tdm2 are cle ared to 0. data loop. enabling of these bits provides a bridge from one dai interface to th e other. data format looping could occur in both directions simultaneously. bit description dl1 = 0 normal operation dl1 = 1, sel2 = 1 enables sdins1 to sdouts2. dl2 = 0 normal operation dl2 = 1, sel1 = 0 enables sdins2 to sdouts1. dl1/2 note: the lrclks1 and lrclks2 interfaces must be identical. set the sel1/2, sdoen1/2, and sdien1/2 bits as shown in the table below to conne ct the s1 and s2 pins to the dai1 and dai2 paths in the max9880a. setting sel1 sel2 sdien1 sdoen1 sdien2 sdoen2 connect s1 pins to dai1 (dac and adc) 0 x 1 1 0 0 connect s2 pins to dai1 (dac and adc) 1 0 1 0 0 1 connect s1 pins (dac only) to dai2 1 0 0 0 1 0 connect s2 pins (dac only) to dai2 x 1 0 0 1 0 connect s1 pins (dac and adc) to dai1, connect s2 to dai2 (dac only) 0 1 1 1 1 0 sel1/sel2 connect s2 pins (dac and adc) to dai1, connect s1 to dai2 (dac only) 1 0 1 0 1 1 sdoen1/2 sdout enable 1 = serial-data output enabled on s1/s2 pins. 0 = serial-data output disabled on s1/s2 pins. sdien1/2 sdin enable 1 = serial-data input to dai1/2 audio path enabled. 0 = serial-data input to dai1/2 audio path disabled. dmono1 mono playback mode 0 = stereo data input on dai1 path is processed separately. 1 = stereo data input on dai1 path is mixed to a single channel and routed to both the left and right dac. when operating in mono voice mode (mode = 1), stereo data may still be inp ut through dai1 path and optionally mixed using dmono1 = 1. table 7. digital audio interface registers (continued) downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec ______________________________________________________________________________________ 35 bits function bclk select. configures bclk when operating in master mode. bsel has no effect i n slave mode. set bsel = 010, unless sharing the bus with multiple devices. bsel description 000 off (bclk output held low) 001 64x lrclk (192x internal clock divided by 3) 010 48x lrclk (192x internal clock divided by 4) 011 128x lrclk ( note: not a valid bsel2 choice when dhf = 1.) 100 pclk/2 101 pclk/4 110 pclk/8 bsel1/2 111 pclk/16 tdm slot select. selects the time slot to use for left/right data according to the following information when operating in time-division multiplex mode. slot description 00 time slot 1 01 time slot 2 10 time slot 3 slotl1/2 slotr1/2 11 time slot 4 slot data delay (slotdly1/slotdly2) in tdm mode: configures the data delay for each slot in tdm mode of operation accordi ng to the following information. in non-tdm mode (tdm = 0): slotdly[1:0] does not have any effect. slotdly1/2[3:0] description 0xxx data for slot 4 begins immediately. 1xxx data for slot 4 delayed 1 bclk cycle. x0xx data for slot 3 begins immediately. x1xx data for slot 3 delayed 1 bclk cycle. xx0x data for slot 2 begins immediately. xx1x data for slot 2 delayed 1 bclk cycle. xxx0 data for slot 1 begins immediately. slotdly1/2 xxx1 data for slot 1 delayed 1 bclk cycle (not valid when fsw = 1). dhf dac high sample rate mode (dhf) (valid only for dai2 audio path) 1 = lrclk is greater than 50khz. 4x fir interpolation filter used. 0 = lrclk is less than 50khz. 8x fir interpolation filter used. table 7. digital audio interface registers (continued) downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec 36 ______________________________________________________________________________________ d15 d14 relative to pclk (see note) 7ns (typ) left 1/f s right d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d14 d15 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d14 d15 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 lrclk audio master modes:left justified: tdm = 0, wci = 0, bci = 0, dly = 0, slotdly = 0 sdout bclk 20ns (min) 5ns (min) configured by bsel sdin left justified + lrclk invert: tdm = 0, wci = 1, bci = 0, dly = 0, slotdly = 0 40ns (max)0ns (min) d15 d14 relative to pclk (see note) left 1/f s right d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d14 d15 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d14 d15 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 lrclk sdout bclk 20ns (min) 5ns (min) configured by bsel sdin 40ns (max)0ns (min) d15 d14 relative to pclk (see note) left 1/f s right d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d14 d15 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d14 d15 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 lrclk sdout bclk 20ns (min) 5ns (min) configured by bsel sdin sdin d14 d15 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 left justified + bclk invert: tdm = 0, wci = 1, bci = 0, dly = 0, slotdly = 0 40ns (max)0ns (min) relative to pclk (see note) left 1/f s right d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 lrclk bclk 20ns (min) 5ns (min) configured by bsel sdin i 2 s: tdm = 0, wci = 1, bci = 0, dly = 0, slotdly = 0 40ns (max)0ns (min) d14 d15 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sdin d14 d15 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 relative to pclk (see note) left 1/f s right d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 lrclk bclk 20ns (min) 5ns (min) configured by bsel sdin left justified: tdm = 0, wci = 1, bci = 0, dly = 0, slotdly = 1 40ns (max)0ns (min) 7ns (typ) 7ns (typ) 7ns (typ) 7ns (typ) 7ns (typ) 7ns (typ) 7ns (typ) 7ns (typ) 7ns (typ) 7ns (typ) 7ns (typ) 7ns (typ) 7ns (typ) 7ns (typ) 7ns (typ) 7ns (typ) 7ns (typ) 7ns (typ) 7ns (typ) note: the delay from a bclk edge and an lrclk edge is determined by length of time that pclk (the internally divided-down version of mclk as defined by the psclk bits) period of mclk plus the internal delay. for example: if f pclk = 12.288mhz, then the delay between bclk and lrclk is typically 45ns. figure 1. digital audio interface audio master mode downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec ______________________________________________________________________________________ 37 d15 d14 20ns (min) left 1/f s right d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d14 d15 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d14 d15 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 lrclk audio slave modes: left justified: tdm = 0, wci = 0, bci = 0, dly = 0, slotdly = 0 sdout bclk 20ns (min) 5ns (min) 75ns (min) 30ns (min) sdin 0ns (min) left justified + lrclk invert: tdm = 0, wci = 1, bci = 0, dly = 0, slotdly = 0 40ns (max)0ns (min) 30ns (min) d15 d14 20ns (min) left 1/f s right d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d14 d15 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d14 d15 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 lrclk sdout bclk 20ns (min) 5ns (min) 75ns (min) 30ns (min) sdin 0ns (min) 40ns (max)0ns (min) 30ns (min) d15d15 d14 20ns (min) left 1/f s right d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d14 d15 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d14 d15 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 lrclk sdout bclk 20ns (min) 5ns (min) 75ns (min) 30ns (min) sdin 0ns (min) d13 d14 d15 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sdin d13 d14 d15 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 left justified + lrclk invert: tdm = 0, wci = 1, bci = 0, dly = 0, slotdly = 0 40ns (max)0ns (min) 30ns (min) 20ns (min) left 1/f s right d14 d15 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 lrclk bclk 20ns (min) 5ns (min) 75ns (min) 30ns (min) sdin 0ns (min) i 2 s: tdm = 0, wci = 0, bci = 0, dly = 1, slotdly = 0 40ns (max)0ns (min) 30ns (min) d14 d15 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sdin d14 d15 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 20ns (min) left 1/f s right d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 lrclk bclk 20ns (min) 5ns (min) 75ns (min) 30ns (min) sdin 0ns (min) left justified: tdm = 0, wci = 1, bci = 0, dly = 0, slotdly = 1 40ns (max)0ns (min) 30ns (min) figure 2. digital audio interface audio slave mode downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec 38 ______________________________________________________________________________________ r14 r15 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 l15 l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 sdout 200ns 1/f s lrclk bclk 20ns (min) 0ns (min) configured by bsel sdin tdm = 1, bci = 1, hizoff = 0, slotdly = 0, slot = 00 40ns (max)0ns (min) 7ns (typ) 7ns (typ) 7ns (typ) voice (tdm/pcm) master modes:tdm = 1, bci = 0, hizoff = 0, slotdly = 0, slot = 00, dly = 0 7ns (typ) r14 r15 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 l15 l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 sdin r14 r15 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 l15 l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 sdout 200ns 1/f s lrclk bclk 20ns (min) 0ns (min) configured by bsel sdin 40ns (max)0ns (min) 7ns (typ) 7ns (typ) 7ns (typ) 7ns (typ) r14 r15 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 l15 l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 r14 r15 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 l15 l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 sdout 200ns 1/f s lrclk bclk 20ns (min) 0ns (min) configured by bsel sdin tdm = 1, bci = 0, hizoff = 1, slotdly = 0, slot = 00, dly = 0 40ns (max)0ns (min) 7ns (typ) 7ns (typ) 7ns (typ) 7ns (typ) r14 r15 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 l15 l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 figure 3. digital audio interface voice master mode downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec ______________________________________________________________________________________ 39 r14 r15 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 l15 l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 sdout 20ns 0ns (min) 0ns (min) 1/f s lrclk bclk 20ns (min) 0ns (min) 75ns (min) sdin tdm = 1, bci = 1, hizoff = 0, slotdly = 0, slot = 00, dly = 0 40ns (max)0ns (min) 30ns (min) 30ns (min) 7ns (typ) voice (tdm/pcm) slave modes: tdm = 1, bci = 0, hizoff = 0, slotdly = 0, slot = 00, dly = 0 r14 r15 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 l15 l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 sdin r14 r15 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 l15 l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 sdout 20ns 0ns (min) 0ns (min) 1/f s lrclk bclk 20ns (min) 0ns (min) 75ns (min) sdin tdm = 1, bci = 0, hizoff = 1, slotdly = 0, slot = 00, dly = 0 40ns (max)0ns (min) 30ns (min) 30ns (min) 7ns (typ) r14 r15 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 l15 l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 sdin r14 r15 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 l15 l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 sdout 20ns 0ns (min) 0ns (min) 1/f s lrclk bclk 20ns (min) 0ns (min) 75ns (min) sdin 40ns (max)0ns (min) 30ns (min) 30ns (min) r14 r15 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 l15 l14 l13 l12 l11 l10 l9 l8 l7 l6 l5 l4 l3 l2 l1 l0 sdin figure 4. digital audio interface voice slave mode register b7 b6 b5 b4 b3 b2 b1 b0 register address (see note) digital mixers dac-l/r mixer mixdal mixdar 0x10 table 8. digital mixers note: register addresses listed are for i 2 c. to get the spi address, add 0x200 with the following exception: register 0xff is not accessible through spi. bits function digital mixers (mixdal/mixdar). selects and mixes the audio source(s) for the dacs according to the information below. mixdal/mixdar source 1xxx dai1 left-channel data x1xx dai1 right-channel data xx1x dai2 left-channel data mixdal/ mixdar xxx1 dai2 right-channel data downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec 40 ______________________________________________________________________________________ code filter type valid sample rate (kh) highpass corner frequency 217h notch 0x0 disabled 0x1 elliptical 16 256hz yes 0x2 butterworth 16 500hz no 0x3 elliptical 8 256hz yes 0x4 butterworth 8 500hz no 0x5 butterworth 8 to 24 f s /240 no 0x6 to 0x7 reserved table 10. iir highpass digital filters digital filtering the max9880a incorporates both iir (voice) and fir(audio) digital filters to accomodate a wide range of audio sources. the iir fiilters provide over 70db of stopband attenuation as well as selectable highpass fil-ters. the fir filters provide low power consumption and are linear phase to maintain stereo imaging. register b7 b6 b5 b4 b3 b2 b1 b0 register address (see note) digital filtering codec filters mode avflt dcb dvflt 0x11 bits function mode digital audio filter mode. selects the filtering mode for the dai1 dac and adc signal paths. 0 = iir voice filters 1 = fir audio filters avflt adc digital audio filter. configures the highpass filters for the dai1 signal path. mode = 0 select the desired digital filter response from table 10. see the frequen cy response graphs in the tpical operating characteristics section for details on each filter. mode = 1 0x0 = dc-blocking filter disabled. 0x1 = dc-blocking filter enabled. dcb 1 = dc-blocking filter for dai2 enabled. 0 = dc-blocking filter for dai2 disabled. dvflt dac digital audio filter. configures the highpass filters for the dai1 signal path. mode = 0 select the desired digital filter response from table 10. see the frequen cy response graphs in the tpical operating characteristics section for details on each filter. mode = 1 0x0 = dc-blocking filter disabled. 0x1 = dc-blocking filter enabled. table 9. digital filtering register note: register addresses listed are for i 2 c. to get the spi address, add 0x200 with the following exception: register 0xff is not accessible through spi. downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec ______________________________________________________________________________________ 41 register b7 b6 b5 b4 b3 b2 b1 b0 register address (see note) configuration spdmclk spdml spdmr 0 0 0 0 0x12 input mixspdml mixspdmr 0x13 bits function spdmclk spdm clock rate (spdmclk) 00 = spdmclk is set to pclk/8. 01 = spdmclk is set to pclk6. 10 = spdmclk is set to pclk/4. 11 = reserved spdml/spdmr 0 = disables spdm data. 1 = enables spdm data. spdm input mixers. selects and mixes the audio source(s) for the spdm output according to following information. mixspdml/mixspdmr source 1xxx dai1 left-channel data x1xx dai1 right-channel data xx1x dai2 left-channel data mixspdml/ mixspdmr xxx1 dai2 right-channel data table 11. spdm output registers grayed boxes = not used. note: register addresses listed are for i 2 c. to get the spi address, add 0x200 with the following exception: register 0xff is not accessible through spi. the max9880a supports stereo pdm outputs. the pdmsignals consist of pdm data outputs (spdmdata) and a clock output (spdmclk). the mixer at the input to the pdm modulators allows a mix/mux of the audio digital datastream from the digital audio ports sdins1 and sdins2. figure 5 shows the spdm interface timing diagram. spdmclk spdmdata left ch right ch left ch right ch t dly, dsd t dly, dsd figure 5. spdm timing diagram downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec 42 ______________________________________________________________________________________ digital gain control the max9880a includes gain adjustment for the play-back and record paths. independent gain adjustment is provided for the two record channels. sidetone gainadjustment is also provided to set the sidetone level rel- ative to the playback level. register b7 b6 b5 b4 b3 b2 b1 b0 register address (see note) level control sidetone dsts 0 dvst 0x15 stereo dac level 0 sdacm 0 0 sdaca 0x16 voice dac level 0 vdacm vdacg vdaca 0x17 left adc level 0 0 avlg avl 0x18 right adc level 0 0 avrg avr 0x19 bits function dsts digital sidetone source mixer 00 = no sidetone selected. 01 = left adc 10 = right adc 11 = left and right adc digital sidetone level control. all gain settings are relative to the adc input voltage. differential headphone output mode setting gain (db) setting gain (db) setting gain (db) 0x00 off 0x0b -20 0x16 -42 0x01 0 0x0c -22 0x17 -44 0x02 -2 0x0d -24 0x18 -46 0x03 -4 0x0e -26 0x19 -48 0x04 -6 0x0f -28 0x1a -50 0x05 -8 0x10 -30 0x1b -52 0x06 -10 0x11 -32 0x1c -54 0x07 -12 0x12 -34 0x1d -56 0x08 -14 0x13 -36 0x1e -58 0x09 -16 0x14 -38 0x1f -60 0x0a -18 0x15 -40 capacitorless and single-ended headphone output mode setting gain (db) setting gain (db) setting gain (db) 0x00 off 0x0b -25 0x16 -47 0x01 -5 0x0c -27 0x17 -49 0x02 -7 0x0d -29 0x18 -51 0x03 -9 0x0e -31 0x19 -53 0x04 -11 0x0f -33 0x1a -55 0x05 -13 0x10 -35 0x1b -57 0x06 -15 0x11 -37 0x1c -59 0x07 -17 0x12 -39 0x1d -61 0x08 -19 0x13 -41 0x1e -63 0x09 -21 0x14 -43 0x1f -65 dvst 0x0a -23 0x15 -45 table 12. digital gain registers grayed boxes = not used. note: register addresses listed are for i 2 c. to get the spi address, add 0x200 with the following exception: register 0xff is not accessible through spi. downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec ______________________________________________________________________________________ 43 bits function sdacm/ vdacm dac mute enable 0 = no mute 1 = mute vdacg dac gain 00 = 0db 01 = +6db 10 = +12db 11 = +18db note: vdacg is only used when mode = 0. if mode = 1, then the dac gain is alway s 0db. dac level control. vdaca/sdaca works in all modes. setting gain (db) setting gain (db) 0x0 0 0x8 -8 0x1 -1 0x9 -9 0x2 -2 0xa -10 0x3 -3 0xb -11 0x4 -4 0xc -12 0x5 -5 0xd -13 0x6 -6 0xe -14 vdaca/sdaca 0x7 -7 0xf -15 adc gain control. applies the specified gain to the digital adc paths according to th e following information. setting gain (db) 0x0 0 0x1 +6 0x2 +12 avlg/avrg 0x3 +18 adc left/right level control setting gain (db) setting gain (db) 0x0 +3 0x8 -5 0x1 +2 0x9 -6 0x2 +1 0xa -7 0x3 0 0xb -8 0x4 -1 0xc -9 0x5 -2 0xd -10 0x6 -3 0xe -11 avl/avr 0x7 -4 0xf -12 table 12. digital gain registers (continued) downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec 44 ______________________________________________________________________________________ line inputs the max9880a include one pair of single-ended lineinputs. when enabled the line inputs connect directly to the headphone amplifier and line outputs and can be optionally connected to the adc for recording. playback volume the max9880a incorporates volume and mute control toallow level control for the playback audio path. program registers 0x1c and 0x1d to set the desired volume. line output level the max9880a incorporates gain and mute control toallow level control for the line outputs. register b7 b6 b5 b4 b3 b2 b1 b0 register address (see note) left-line input level 0 lilm 0 0 ligl 0x1a right-line input level 0 lirm 0 0 ligr 0x1b bits function lilm/lirm line input left/right playback mute 0 = line input is connected to the headp hone amplifiers. 1 = line input is disconnected from the headp hone amplifiers. line input left/right gain setting gain (db) setting gain (db) 0x0 +24 0x8 +8 0x1 +22 0x9 +6 0x2 +20 0xa +4 0x3 +18 0xb +2 0x4 +16 0xc 0 0x5 +14 0xd -2 0x6 +12 0xe -4 ligl/ligr 0x7 +10 0xf -6 table 13. line input registers register b7 b6 b5 b4 b3 b2 b1 b0 register address (see note) left volume control 0 vollm voll 0x1c right volume control 0 volrm volr 0x1d bits function vollm/ volrm left/right playback mute. vollm and volrm mute both the dac and line input audio signals. 0 = audio playback is unmuted. 1 = audio playback is muted. note: vsen has no effect on the mute function. when vollm or volrm is set, the output i s muted immediately ( zden = 1) or at the next zero-crossing ( zden = 0). table 14. playback volume registers grayed boxes = not used. note: register addresses listed are for i 2 c. to get the spi address, add 0x200 with the following exception: register 0xff is not accessible through spi. grayed boxes = not used. note: register addresses listed are for i 2 c. to get the spi address, add 0x200 with the following exception: register 0xff is not accessible through spi. downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec ______________________________________________________________________________________ 45 bits function left/right playback volume. voll and volr control the playback volume for both the dac and line in put audio signals. setting gain (db) setting gain (db) setting gain (db) 0x00 +9 0x0e -2 0x1c -39 0x01 +8.5 0x0f -3 0x1d -43 0x02 +8 0x10 -5 0x1e -47 0x03 +7.5 0x11 -7 0x1f -51 0x04 +7 0x12 -9 0x20 -55 0x05 +6.5 0x13 -11 0x21 -59 0x06 +6 0x14 -13 0x22 -63 0x07 +5 0x15 -15 0x23 -67 0x08 +4 0x16 -17 0x24 -71 0x09 +3 0x17 -19 0x25 -75 0x0a +2 0x18 -23 0x26 -79 0x0b +1 0x19 -27 0x27 -81 0x0c 0 0x1a -31 0x0d -1 0x1b -35 0x28 to 0x3f mute voll/volr note: gain settings apply when the headphone amplifier is configured i n differential mode. in the single- ended and capacitorless modes, the actual gain is 5db lower. assuming logl/logr = 0db, line output gain is 6db lower. table 14. playback volume registers (continued) register b7 b6 b5 b4 b3 b2 b1 b0 register address (see note) left-line output level 0 lolm 0 0 logl 0x1e right-line output level 0 lorm 0 0 logr 0x1f bits function lolm/lorm left/right line output mute. lolm and lorm mute both the dac and line input audio signals. 0 = line output is unmuted. 1 = line output is muted. note: vsen has no effect on the mute function. when lolm or lorm is set the output is muted immediately ( zden = 1) or at the next zero-crossing ( zden = 0). left/right line output gain. logl and logr set the line output gain according to the following informa tion. setting gain (db) setting gain (db) 0x00 0 0x08 -16 0x01 -2 0x09 -18 0x02 -4 0x0a -20 0x03 -6 0x0b -22 0x04 -8 0x0c -24 0x05 -10 0x0d -26 0x06 -12 0x0e -28 logl/logr 0x07 -14 0x0f -30 table 15. output line-level registers grayed boxes = not used. note: register addresses listed are for i 2 c. to get the spi address, add 0x200 with the following exception: register 0xff is not accessible through spi. downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec 46 ______________________________________________________________________________________ microphone inputs two differential microphone inputs and a low noise 1.5vmicrophone bias for powering the microphones are provided by the max9880a. in typical applications, the left microphone records a voice signal and the right microphone records a background noise signal. in applications that require only one microphone, use the left microphone input and disable the right adc. the microphone signals are amplified by two stages of gainand then routed to the adcs. the first stage offers selectable 0db, 20db, or 30db settings. the second stage is a programmable gain amplifier (pga) adjustable from 0db to 20db in 1db steps. zero-cross- ing detection is included on the pga to minimize zipper noise while making gain changes. see figure 6 for a detailed diagram of the microphone input structure. register b7 b6 b5 b4 b3 b2 b1 b0 register address (see note) left microphone gain 0 palen pgaml 0x20 right microphone gain 0 paren pgamr 0x21 bits function palen/ paren left/right microphone preamplifier gain. enables the microphone circuitry and sets the preamplifier gain. 00 = disabled01 = 0db 10 = +20db 11 = +30db table 16. microphone input registers micln miclp micbias pgapga - preamp micrn adc l adc r micrp 1.5v 0/20/30db 0db to +20db0db to +20db v reg v reg 0/20/30db preamp max9880a figure 6. microphone input block diagram grayed boxes = not used. note: register addresses listed are for i 2 c. to get the spi address, add 0x200 with the following exception: register 0xff is not accessible through spi. downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec ______________________________________________________________________________________ 47 bits function left/right microphone programmable gain amplifier setting gain (db) setting gain (db) 0x00 +20 0x0b +9 0x01 +19 0x0c +8 0x02 +18 0x0d +7 0x03 +17 0x0e +6 0x04 +16 0x0f +5 0x05 +15 0x10 +4 0x06 +14 0x11 +3 0x07 +13 0x12 +2 0x08 +12 0x13 +1 0x09 +11 0x14 to 0x1f 0 pgaml/ pgamr 0x0a +10 table 16. microphone input registers (continued) adc the max9880a includes two 18-bit adcs. the firstadc is used to record left-channel microphone and line-input audio signals. the second adc can be used to record right-channel microphone and line-input sig- nals or it can be configured to accurately measure dc voltages. when measuring dc voltages both the left and right adc must be enabled by setting adlen and adren in regis- ter 0x26. the input to the second adc is jacksns/ aux and the output is reported in aux (registers 0x02 and 0x03). since the audio adc is used to perform the measurement, the digital audio interface must be prop- erly configured. if the left adc is being used to convert audio, then the dc measurement is performed at the same sample rate. when not using the left adc, config- ure the digital interface for a 48khz sample rate to ensure the fastest possible settling time. to ensure accurate results, the max9880a includes two calibration routines. calibrate the adc each time the max9880a is powered on. calibration settings are not lost if the max9880a is placed in shutdown. when making a measurement, set auxcap to 1 to prevent aux from changing while reading the registers. setup procedure 1) ensure a valid mclk signal is provided and config- ure psclk appropriately. 2) choose a clocking mode. the following options are possible:a. slave mode with lrclk and bclk signalsprovided. the measurement sample rate is determined by the external clocks. b. slave mode with no lrclk and bclk signalsprovided. configure the device for normal clock mode using the ni ratio. select f s = 48khz to allow for the fastest settling times. c. master mode with audio. configure the device in normal mode using the ni ratio or exact inte-ger mode using freq1 as required by the audio signal. d. master mode without audio. configure the device in normal mode using the ni ratio. selectf s = 48khz to allow for the fastest settling times. 3) ensure jack sense is disabled. 4) enable the left and right adc; take the max9880a out of shutdown. downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec 48 ______________________________________________________________________________________ offset calibration procedure perform before the first dc measurement is taken afterapplying power to the max9880a. 1) enable the aux input (auxen = 1). 2) enable the offset calibration (auxcal = 1). 3) wait the appropriate time (see table 17). 4) complete calibration (auxcal = 0). gain calibration procedure perform the first time a dc measurement is taken afterapplying power to the max9880a or if the temperature changes significantly. 1) enable the aux input (auxen = 1). 2) start gain calibration (auxgain = 1). 3) wait the appropriate time (see table 17). 4) freeze the measurement results (auxcap = 1). 5) read aux and store the value in memory to correct all future measurements (k = aux[15:0], k is typical-ly 19,500). 6) complete calibration (auxgain = auxcap = 0). dc measurement procedure perform after offset and gain calibration are complete. 1) enable the aux input (auxen = 1). 2) wait the appropriate time (see table 17). 3) freeze the measurement results (auxcap = 1). 4) read aux and correct with the gain calibration value 5) complete measurement (auxcap = 0). complete dc measurement example f mclk = 13mhz, slave mode, bclk, and lrclk are not externally supplied. 1) configure the digital audio interface for f s = 48khz (psclk = 01, freq1 = 0x0, pll = 0, ni = 0x5abe,mas = 0). 2) disable jack sense (jdeten = 0). 3) enable the left and right adc; take the max9880a out of shutdown (adlen = adren = shdn = 1). 4) calibrate the offset: a. enable the aux input (auxen = 1).b. enable the offset calibration (auxcal = 1). c. wait 40ms. d. complete calibration (auxcal = 0). 5) calibrate the gain: a. start gain calibration (auxgain = 1).b. wait 40ms. c. freeze the measurement results (auxcap = 1). d. read aux and store the value in memory to cor- rect all future measurements (k = aux[15:0]). e. complete calibration (auxgain = auxcap = auxen = 0). 6) measure the voltage on jacksns/aux. a. enable the aux input (auxen = 1).b. wait 40ms. c. freeze the measurement results (auxcap = 1). d. read aux and correct with the gain calibration value. e. complete measurement (auxcap = 0). 7) dc measurement is complete. v aux k aux = ? ? ? ? ? ? ? ? ? ? ? ? 0 738 15 0 . [:] . lrclk (kh) wait time (ms) 48 40 44.1 44 32 60 24 80 22.05 90 16 120 12 160 11.025 175 8 240 table 17. aux adc wait times downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec ______________________________________________________________________________________ 49 register b7 b6 b5 b4 b3 b2 b1 b0 register address (see note) input mxinl mxinr auxcap auxgain auxcal auxen 0x22 bits function mxinl/mxinr left/right adc audio input mixer 00 = no input selected 01 = left/right analog microphone 10 = left/right line input 11 = left/right analog microphone + line input note: if the right line input is disabled, then the left line input is connected to both mixers. enabling the left and right digital microphones disables the left and right audio mixer , respectively. see the digmicl/ digmicr bit description for more details. auxcap auxiliary input capture 0 = update aux with the voltage at jacksns/aux. 1 = hold aux for reading. auxgain auxiliary input gain calibration 0 = normal operation 1 = the input buffer is disconnected from jacksns/aux and connected to an internal voltage reference. while in this mode, read the aux register and store the value. us e the stored value as a gain calibration factor, k, on subsequent readings. auxcal must remain set for time indicated in table 17 to guarantee an accurate offset calibration. auxcal auxiliary input offset calibration 0 = normal operation 1 = jacksns/aux is disconnected from the input and the adc automatical ly calibrates out any internal offsets. auxcal must remain set for time indicated in table 17 to guara ntee an accurate offset calibration. auxen auxiliary input enable 0 = use jacksns/aux for jack detection. 1 = use jacksns/aux for dc measurements. note: set mxinr = 00, adlen = 1, and adren = 1 when auxen = 1. table 18. adc input register note: register addresses listed are for i 2 c. to get the spi address, add 0x200 with the following exception: register 0xff is not accessible through spi. downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec 50 ______________________________________________________________________________________ digital microphone input the max9880a can accept audio from up to two digi-tal microphones. when using digital microphones, the left analog microphone input is retasked as a digital microphone input. the right analog microphone input isstill available to allow a combination of analog and digi- tal microphones to be used. figure 7 shows the digital microphone interface timing diagram. digmicclk digmicdata t su, mic t hd, mic t su, mic t hd, mic left right left right 1/f micclk figure 7. digital microphone timing diagram register b7 b6 b5 b4 b3 b2 b1 b0 register address (see note) microphone micclk digmicl digmicr 0 0 0 mbias 0x23 bits function micclk digital microphone clock 00 = pclk/8 01 = pclk/6 10 = 64f s (high jitter clock) 11 = reserved digital left/right microphone enable digmicl digmicr left adc input right adc input 0 0 adc input mixer adc input mixer 0 1 line input (left analog microphone unavailable) right digital microphone 1 0 left digital microphone adc input mixer 1 1 left digital microphone right digital microphone digmicl/ digmicr note: the left analog microphone input is never available when digmicl or di gmicr = 1. mbias microphone bias output voltage set mbias = 0 for nominal output of 1.52v (v micvdd = 1.8v) set mbias = 1 for nominal output of 2.2v (v micvdd = 3v) table 19. digital microphone input register grayed boxes = not used. note: register addresses listed are for i 2 c. to get the spi address, add 0x200 with the following exception: register 0xff is not accessible through spi. downloaded from: http:///
jack configuration change flag (jdet) 1 = jack configuration has changed.0 = no change in jack configuration. jdet reports changes in jksns[1:0]. changes to jksns[1:0] are debounced before setting jdet. the debounce period is programmable using the jdeb bits. jack status register 0x01 is a read-only register that reports the status of the jack-detect circuitry when enabled. jack sense (jksns) jksns[1:0] reports the status of the jacksns pinwhen jdeten = 1. jksns[1:0] should be interpreted according to table 21. jack-detect interrupt enable (ijdet) hardware interrupts are reported on the open-drain irq pin. when an interrupt occurs, irq remains low until the interrupt is serviced by reading the status register 0x00.if a flag is set, it is reported as a hardware interrupt only if the corresponding interrupt enable is set. each bit enables interrupts for the status flag in the respective bit location in register 0x00. so ijdet must be set to enable interrupts for jack detect. jack-detect enable (jdeten) enables the jack-detect circuitry. jack-sense weak pullup (jdwk) enables a weak internal pullup current for reducedpower loss when the chip is in shutdown or the micbias is disabled. jdwk = 0 enables a 2.2k ? pullup to obtain full jack- detect operation. this mode can be used to detectinsertion and removal of a plug as well as distinguish between headphone and headset accessories. jdwk = 1 enables a 4? pullup current source when shdn = 0 or micbias disabled. in this power-saving configuration, the circuit can detect insertion andremoval of a plug but cannot distinguish between head- phone and headset accessories. the recommended usage follows: set jdwk = 0 (or set any bit in the microphone preamplifier gain registers palen[1:0] or paren[1:0]). this enables the 2.2k ? pullup. once the jack has been inserted and the type ofaccessory determined, set jdwk = 1 to save power. once the plug is removed, set jdwk = 0. max9880a low-power, high-performance dual i 2 s stereo audio codec ______________________________________________________________________________________ 51 mode configuration the max9880a includes circuitry to minimize click-and-pop during volume changes, detect headsets, and con- figure the headphone amplifier mode. both volume slewing and zero-crossing detection are included to ensure click-and-pop free volume transitions. headset detection overview the max9880a contains headset detect circuitry that iscapable of detecting the insertion or removal of a plug and providing information to assist the system controllerin determining the configuration of an inserted plug. if programmed to do so, upon insertion or removal of a plug, the irq output is asserted (pulled low). table 20 shows the registers associated with the jackdetect function in max9880a. table 21. jack sense (jksns) table 20. jack-detect registers register b7 b6 b5 b4 b3 b2 b1 b0 register address por state r/w status cld sld ulk * * jdet 0x00 r jack status jksns[1:0] 0x01 r interrupt enable icld isld iulk 0 0* 0* ijdet 0 0x04 0x00 r/w jack detect jdeten 0 jdwk 0 0 0 jdeb 0x25 0x00 r/w jksns[1:0] description 00 jacksns is below v th2 (low). 01 jacksns is between v th1 and v th2 (mid). 10 invalid. 11 jacksns is above v th1 (high). grayed boxes = not used. downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec 52 ______________________________________________________________________________________ mic gnd hpr hpl loutproutp micbiasjacksns/aux miclp figure 8. typical configuration for headset detection debounce (jdeb) configures the jdet debounce time for changes tojksns[1:0] according to table 22. for jack plug insertion/removal, the sequence of events is as follows: jack insertion: no jack is present. the max9880a has a power supply and is in low-power sleep mode(loutp/routp are high impedance). when the jdeten i 2 c bit is set, the jacksns pin has weak pullups to micvdd. when a jack is subsequently insert-ed, jacksns should change state (indicated by i 2 c bits jksns[1:0]), and this causes the irq pin to be pulled low, which can trigger a system wakeup.jack present: after an interrupt has been sent to the system controller, the i 2 c must indicate unambiguously that a jack is present when the i 2 c registers are read. this is done with the jdet i 2 c bit, which goes high when there is a change of state of the jksns[1:0] bits.the max9880a jack-detect system monitors the jacksns pin and reports the voltage level as high (> 95% x micbias), mid, or low (< 10% x micbias). when connected to the microphone pin of the headset jack, this window comparator allows detection of: no headset (high) cellular headset with microphone (high mid) stereo headset without microphone (high low) cellular headset button press (mid low mid) headset removal (low or mid high) jack removal: a jack is present. all output poles (headphones/line outs) are assumed driven by a lowimpedance amplifier. all input poles (microphones) are assumed to be biased with a voltage above ground but below 95% of the micbias voltage. for the max9880a to sense when a jack is removed, the jacksns pin must be connected to the jack in such a way as to ensure either the jacksns pin gets pulled above 95% of micbias (as would happen if jacksns is hooked to a microphone pole) or it changes state from low to high or vice versa (as would happen if jacksns is hooked to a ground pole which goes high impedance when the jack is removed, or is hooked to a regular jack insertion tab that shorts to ground when the jack is removed). subsequently, irq is pulled low. jack absent: after an interrupt has been sent to the system controller, the i 2 c must indicate unambiguously that a jack is not present when the i 2 c registers are read. this is indicated by reading the status of thejksns[1:0] i 2 c read bits. table 22. debounce time jdeb debounce (ms) 00 25 01 50 10 100 11 200 downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec ______________________________________________________________________________________ 53 table 23. headset detect configuration jack action jksns irq toggles? shdn micbias jdwk from to from to ijdet = 1 ijdet = 0 0 0 none headset 11 01 yes no 0 0 none headphone 11 00 yes no 0 0 headset none 01 11 yes no 0 0 headphone none 00 11 yes no 0 1 none headset 11 00 yes no 0 1 none headphone 11 00 yes no 0 1 headset none 00 11 yes no 0 1 headphone none 00 11 yes no 1 0 0 none headset 11 01 yes no 1 0 0 none headphone 11 00 yes no 1 0 0 headset none 01 11 yes no 1 0 0 headphone none 00 11 yes no 1 0 1 none headset 11 00 yes no 1 0 1 none headphone 11 00 yes no 1 0 1 headset none 00 11 yes no 1 0 1 headphone none 00 11 yes no 1 1 none headset 11 01 yes no 1 1 none headphone 11 00 yes no 1 1 headset none 01 11 yes no 1 1 headphone none 00 11 yes no note: jdeten = 1; micbias enable; any bit of palen/paren set. downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec 54 ______________________________________________________________________________________ loutp loutn routp routn differential loutp loutn routp routn capacitorless 1 f loutp 220 f loutn single-ended 1 f routp 220 f routn optional components required for click-and-pop suppression only. figure 9. headphone amplifier modes register b7 b6 b5 b4 b3 b2 b1 b0 register address (see note) mode dslew vsen zden 0 0 hpmode 0x24 jack detect jdeten 0 jdwk 0 0 0 jdeb 0x25 bits function dslew digital volume slew speed 0 = digital volume changes are slewed over 10ms. 1 = digital volume changes are slewed over 80ms. vsen volume change smoothing 0 = volume changes slew through all intermediate values. 1 = volume changes occur in one step. zden line input zero-crossing detection 0 = line input volume changes occur at zero crossings in the audio wave form or after 62ms if no zero crossing occurs. 1 = line input volume changes occur immediately. table 24. mode configuration register headphone modes the max9880a? headphone amplifier supports differen-tial, single-ended, and capacitorless output modes, as shown in figure 9. in each mode, the amplifier can be configured for stereo or mono operation. the single- ended m ode optionally includes click-and-pop reduc- tion to eliminate the click-and-pop that would normallybe caused by the output coupling capacitor. when click-and-pop reduction is not required leave loutn and routn unconnected. grayed boxes = not used. note: register addresses listed are for i 2 c. to get the spi address, add 0x200 with the following exception: register 0xff is not accessible through spi. downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec ______________________________________________________________________________________ 55 bits function headphone amplifier mode hpmode mode 000 stereo differential 001 mono (left) differential 010 stereo capacitorless 011 mono (left) capacitorless 100 stereo single-ended (clickless) 101 mono (left) single-ended (clickless) 110 stereo single-ended (fast turn-on) 111 mono (left) single-ended (fast turn-on) hpmode note: in mono operation, the right amplifier is disabled. jdeten jack-detection enable shdn = 0: sleep mode. enables pullups on jacksns/aux to detect jack insertion. shdn = 1: normal mode. enables the comparator circuitry on jacksns/aux to detect voltage changes. note: auxen must be set to 0 for jack detection to function. jdwk jack-sense weak pullup. enables an internal pullup. set jdwk = 1 to enable an internal 4a cu rrent source. set jdwk = 0 for external pullup. jack detect debounce. configures the jdet debounce time for changes to jksns[1:0] according to information below. jdeb debounce time (ms) 00 25 01 50 10 100 jdeb 11 200 table 24. mode configuration register (continued) power management the max9880a includes complete power managementcontrol to minimize power usage. the dac and both adcs can be independently enabled so that only the required circuitry is active. revision code the max9880a includes a revision code to allow easyidentification of the device revision. revision code at register address 0xff is not accessible through the spi interface and so the revision code is accessible through spi at an additional address of 0x214. the cur- rent revision code is 0x42. downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec 56 ______________________________________________________________________________________ register b7 b6 b5 b4 b3 b2 b1 b0 register address (see note) enable lnlen lnren lolen loren dalen daren adlen adren 0x26 system shutdown shdn 0 0 0 xten xtosc 0 0 0x27 bits function lnlen left-line input enable . enables the left-line input preamp and automatically enables the left and right headphone amplifiers. if lnren = 0, the left-line input signal is also routed to the right adc input mixer and right headphone amplifier. note: control of the right headphone amplifier can be overridden by hpmode. lnren right-line input enable . enables the right-line input preamp and automatically enables the righ t headphone amplifiers. note: control of the right headphone amplifier can be overridden by hpmode. lolen left-line output enable . enables the left-line output. loren right-line output enable . enables the right-line output. dalen left dac enable . enables the left dac and automatically enables the left and right h eadphone amplifiers. if daren = 0, the left dac signal is also routed to the right headphone amplif ier. note: control of the right headphone amplifier can be overridden by hpmode. daren right dac enable . enables the right dac. right dac operation requires dalen = 1. adlen left adc enable. adren right adc enable. enabling the right adc must be done in the same i 2 c write operation that enables the left adc. the right adc can be enabled while the left adc is running if used for dc measurements. shdn must be toggled to disable the right adc in this case. right adc operation requ ires adlen = 1. shdn shutdown . places the device in low power shutdown mode. xten crystal clock enable 1 = output of crystal oscillator and buffer routed to the clock prescaler. mclk i nput disabled. 0 = mclk input routed to the clock prescaler. crystal osc illator and buffer disabled. xtosc crystal clock source 1 = disables the internal crystal oscillator. provide an external cloc k on x1. 0 = enables the internal crystal oscillator. attach a crystal between x1 and x2. xtosc is ignored if xten = 0. table 25. power management register register b7 b6 b5 b4 b3 b2 b1 b0 register address (see note) revision id rev 0x14 revision id rev 0xff table 26. revision code register grayed boxes = not used. note: register addresses listed are for i 2 c. to get the spi address, add 0x200 with the following exception: register 0xff is not accessible through spi. note: register addresses listed are for i 2 c. to get the spi address, add 0x200 with the following exception: register 0xff is not accessible through spi. downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec ______________________________________________________________________________________ 57 cs sclk din dout t css t ch t dh t ds t do t dz t den t cl t csh t cp t csw figure 10. spi interface timing diagram cs sclk din dout high-z r/w addr9 addr0 unused4 unused0 d7 d0 1 data byte figure 11. writing 1 byte of data to the max9880a serial peripheral interface (spi) chip select ( cs ) the max9880a spi interface is active only when cs is low. when cs is high, the max9880a configures the dout output for high impedance and resets the inter-nal spi logic. if cs goes high in the middle of an spi transfer, all the data is discarded. when cs is low, unless the register address is correctly decoded by themax9880a, the dout output is high impedance. serial clock (sclk) the spi master provides the sclk signal to clock thespi interface. sclk has an upper frequency limit of 25mhz. the max9880a samples the din input data on the falling edge of sclk and changes the output data on the rising edge of sclk. the max9880a ignores sclk transitions when cs is high. serial-data in (din) and serial-data out (dout) the spi frame is organized into 24 bits. the first 16 bitsconsist of the r /w enable bit, followed by the 10 regis- ter address bits and 5 unused bits. the next 8 bits aredata bits, sent most significant bit first. for an spi write transfer, write a 1 to the r /w bit, fol- lowed by the 10 register address bits, 5 unused bits,then the 8 data bits. figure 11 illustrates the proper frame format for writing one byte of data to the max9880a. additional 24-bit frames can be sent while cs remains low. the dout output is high impedance during a write operation.for an spi read transfer, write a zero to the r /w bit, fol- lowed by the 10 register address bits and 5 unusedbits. any data sent after the register address bits are ignored. the internal contents of the register being read downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec 58 ______________________________________________________________________________________ cs sclk din dout high-z r/w addr9 addr0 unused4 unused0 d7 d0 1 data byte figure 12. reading 1 byte of data from the max9880a sclk din dout high-z r/w addr9 addr0 unused4 unused0 d7 d0 1 data byte 1 data byte cs d7 d0 autoincrement internal register address pointer figure 13. reading n bytes of data from the max9880a smbus is a trademark of intel corp. do not change until the transfer is complete. the doutoutput is high impedance when writing the register address bits. if the correct register address is decod- ed, dout is driven low at the first rising clock edge after the first unused bit. figure 12 illustrates the proper frame format for reading 1 byte of data from the max9880a. when reading data from the max9880a, the address pointer autoincrements by one register address if cs is held low after reading the first 8 data bits. for eachsubsequent eight clock cycles, a byte of data is read. this autoincrement feature allows a master to read sequential registers within one continuous spi register address range from 0x200 to 0x227. the register address does not autoincrement if a read is initiated at a register address lower than 0x200. if the register address increments beyond 0x227, the dout output is high impedance. figure 13 illustrates the proper format for reading multiple bytes of data. i 2 c serial interface the max9880a features an i 2 c/smbus-compatible, 2-wire serial interface consisting of a serial-data line(sda) and a serial-clock line (scl). sda and scl facilitate communication between the max9880a and the master at clock rates up to 400khz. figure 14 shows the 2-wire interface timing diagram. the master generates scl and initiates data transfer on the bus. the master device writes data to the max9880a by transmitting the proper slave address followed by the register address and then the data word. each transmit sequence is framed by a start (s) or repeated start (sr) condition and a stop (p) condition. each word transmitted to the max9880a is 8 bits long and is followed by an acknowledge clock pulse. a master reading data from the max9880a transmits the proper slave address followed by a series of nine scl pulses. the max9880a transmits data on sda in sync with the master-generated scl pulses. the master acknowl- edges receipt of each byte of data. each read downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec ______________________________________________________________________________________ 59 scl sda t r t f t buf start condition stop condition repeated start condition start condition t su,sto t hd,sta t su,sta t hd,dat t su,dat t low t high t hd,sta t sp figure 14. 2-wire interface timing diagram scl sda ss rp figure 15. start, stop, and repeated start conditions sequence is framed by a start or repeated startcondition, a not acknowledge, and a stop condition. sda operates as both an input and an open-drain out- put. a pullup resistor, typically greater than 500 ? , is required on sda. scl operates only as an input. apullup resistor, typically greater than 500 ? , is required on scl if there are multiple masters on the bus, or if thesingle master has an open-drain scl output. series resistors in line with sda and scl are optional. seriesresistors protect the digital inputs of the max9880a from high voltage spikes on the bus lines and minimize crosstalk and undershoot of the bus signals. bit transfer one data bit is transferred during each scl cycle. thedata on sda must remain stable during the high period of the scl pulse. changes in sda while scl is high are control signals (see the start and stop conditions section). start and stop conditions sda and scl idle high when the bus is not in use. amaster initiates communication by issuing a start condition. a start condition is a high-to-low transition on sda with scl high. a stop condition is a low-to- high transition on sda while scl is high (figure 15). a start condition from the master signals the beginning of a transmission to the max9880a. the master termi- nates transmission and frees the bus by issuing a stop condition. the bus remains active if a repeated start condition is generated instead of a stop condition. early stop conditions the max9880a recognizes a stop condition at anypoint during data transmission except if the stop con- dition occurs in the same high pulse as a start condi- tion. for proper operation, do not send a stop condition during the same scl high pulse as the start condition. downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec 60 ______________________________________________________________________________________ 1 scl start condition sda 29 clock pulse for acknowledgment acknowledge not acknowledge figure 16. acknowledge a 0 slave address register address data byte acknowledge from max9880a r/w 1 byte autoincrement internal register address pointer acknowledge from max9880a acknowledge from max9880a b1 b0 b3 b2 b5 b4 b7 b6 s a a p figure 17. writing 1 byte of data slave address the slave address is defined as the seven most signifi-cant bits (msbs) followed by the read/write bit. for the max9880a, the seven most significant bits are 0010000. setting the read/write bit to 1 (slave address = 0x21) configures the max9880a for read mode. setting the read/write bit to 0 (slave address = 0x20) configures the max9880a for write mode. the address is the first byte of information sent to the max9880a after the start condition. acknowledge the acknowledge bit (ack) is a clocked 9th bit that themax9880a uses to handshake receipt each byte of data when in write mode (see figure 16). the max9880a pulls down sda during the entire master- generated 9th clock pulse if the previous byte is suc- cessfully received. monitoring ack allows for detection of unsuccessful data transfers. an unsuccessful data transfer occurs if a receiving device is busy or if a sys- tem fault has occurred. in the event of an unsuccessful data transfer, the bus master retries communication. the master pulls down sda during the 9th clock cycleto acknowledge receipt of data when the max9880a is in read mode. an acknowledge is sent by the master after each read byte to allow data transfer to continue. a not acknowledge is sent when the master reads the final byte of data from the max9880a, followed by a stop condition. write data format a write to the max9880a includes transmission of astart condition, the slave address with the r/ w bit set to 0, 1 byte of data to configure the internal registeraddress pointer, 1 or more bytes of data, and a stop condition. figure 17 illustrates the proper frame format for writing 1 byte of data to the max9880a. figure 18 illustrates the frame format for writing n bytes of data to the max9880a. the slave address with the r/ w bit set to 0 indicates that the master intends to write data to the max9880a.the max9880a acknowledges receipt of the address byte during the master-generated 9th scl pulse. downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec ______________________________________________________________________________________ 61 1 byte autoincrement internal register address pointer acknowledge from max9880a acknowledge from max9880a b1 b0 b3 b2 b5 b4 b7 b6 a a 0 acknowledge from max9880a r/w s a 1 byte acknowledge from max9880a b1 b0 b3 b2 b5 b4 b7 b6 p a slave address register address data byte 1 data byte n figure 18. writing n bytes of data acknowledge from max9880a 1 byte autoincrement internal register address pointer acknowledge from max9880a not acknowledge from master a a a p a 0 acknowledge from max9880a r/w s r/w repeated start sr 1 slave address register address slave address data byte figure 19. reading 1 byte of data the second byte transmitted from the master config-ures the max9880a? internal register address pointer. the pointer tells the max9880a where to write the next byte of data. an acknowledge pulse is sent by the max9880a upon receipt of the address pointer data. the third byte sent to the max9880a contains the data that is written to the chosen register. an acknowledge pulse from the max9880a signals receipt of the data byte. the address pointer autoincrements to the next register address after each received data byte. this autoincrement feature allows a master to write to sequential registers within one continuous frame. the master signals the end of transmission by issuing a stop condition. register addresses greater than 0x17 are reserved. do not write to these addresses. read data format send the slave address with the r/ w bit set to 1 to initi- ate a read operation. the max9880a acknowledgesreceipt of its slave address by pulling sda low during the 9th scl clock pulse. a start command followed by a read command resets the address pointer to reg- ister 0x00. the first byte transmitted from the max9880a is the contents of register 0x00. transmitted data is valid on the rising edge of scl. the address pointer autoincre-ments after each read data byte. this autoincrement feature allows all registers to be read sequentially within one continuous frame. a stop condition can be issued after any number of read data bytes. if a stop condi- tion is issued followed by another read operation, the first data byte to be read is from register 0x00. the address pointer can be preset to a specific register before a read command is issued. the master presets the address pointer by first sending the max9880a? slave address with the r/ w bit set to 0 followed by the register address. a repeated start condition is thensent followed by the slave address with the r/ w bit set to 1. the max9880a then transmits the contents of thespecified register. the address pointer autoincrements after transmitting the first byte. the master acknowledges receipt of each read byte during the acknowledge clock pulse. the master must acknowledge all correctly received bytes except the last byte. the final byte must be followed by a not acknowledge from the master and then a stop condi- tion. figure 19 illustrates the frame format for reading 1 byte from the max9880a. figure 20 illustrates the frame format for reading multiple bytes from the max9880a. downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec 62 ______________________________________________________________________________________ acknowledge from max9880a 1 byte autoincrement internal register address pointer acknowledge from max9880a a a a not acknowledge from master a p 0 acknowledge from max9880a r/w s r/w repeated start sr 1 slave address register address slave address data byte figure 20. reading n bytes of data sequence description registers 1 shdn = 0 0x27 2 configure clocks 0x05, 0x06, 0x07, 0x0b, 0x0c 3 configure digital audio interface 0x08, 0x09, 0x0a, 0x0d, 0x0e, 0x0 f table 27. clock initialization (perform before any playback or record setup) sequence description registers 1 select dac audio source 0x10 2 select music filters 0x11 3 set output volume 0x1c, 0x1d 4 set line output volume 0x1e, 0x1f 5 select headphone mode 0x24 6 enable line outputs and dac as required 0x26 7 enable lrclk and bclk (if operating in slave mode) n/a 8 enable max9880a 0x27 9 enable external amplifier (if using) n/a table 28. music playback applications information proper layout and grounding are essential for optimumperformance. when designing a pcb for the max9880a, partition the circuitry so that the analog sections of the max9880a are separated from the digi- tal sections. this ensures that the analog audio traces are not routed near digital traces. use a large continuous ground plane on a dedicated layer of the pcb to minimize loop areas. connect agnd and dgnd directly to the ground plane using the shortest trace length possible. proper grounding improves audio performance, minimizes crosstalk between channels, and prevents any digital noise from coupling into the analog audio signals. ground the bypass capacitors on micbias, reg, preg, and ref directly to the ground plane with mini- mum trace length. also be sure to minimize the path length to agnd. bypass avdd directly to agnd. connect all digital i/o termination to the ground planewith minimum path length to dgnd. bypass dvdd and dvdds1 directly to dgnd. route microphone signals from the microphone to the max9880a as a differential pair, ensuring that the posi- tive and negative signals follow the same path as closely as possible with equal trace length. when using single-ended microphones or other single-ended audio sources, ground the negative microphone input as close to the audio source as possible and then treat the positive and negative traces as differential pairs. the max9880a tqfn package features an exposed thermal pad on its underside. connect the exposed thermal pad to agnd. an evaluation kit (ev kit) is available to provide an example layout for the max9880a. the ev kit allows quick setup of the max9880a and includes easy-to-use software allowing all internal registers to be controlled. startup sequences downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec ______________________________________________________________________________________ 63 sequence description registers 1 set line input gain 0x1a, 0x1b 2 set volume 0x1c, 0x1d 3 set line output volume (if using) 0x1e, 0x1f 4 select headphone mode 0x24 5 enable line outputs and line inputs as required 0x26 6 enable max9880a 0x27 7 enable external amplifier (if using) n/a table 29. line input playback sequence description registers 1 select music filters 0x11 2 set line input gain 0x1a, 0x1b 3 set volume 0x1c, 0x1d 4 set line output volume (if using) 0x1e, 0x1f 5 configure adc input mixer 0x22 6 select headphone mode 0x24 7 enable line outputs, line inputs, and adc as required 0x26 8 enable lrclk and bclk (if operating in slave mode) n/a 9 enable max9880a 0x27 10 enable external amplifier (if using) n/a table 30. line input playback with record sequence description registers 1 select dac audio source 0x10 2 select voice filters 0x11 3 set volume 0x1c, 0x1d 4 set line output volume (if using) 0x1e, 0x1f 5 select headphone mode 0x24 6 enable line outputs and dac as required 0x26 7 enable lrclk and bclk (if operating in slave mode) n/a 8 enable max9880a 0x27 9 enable external amplifier (if using) n/a table 31. voice playback downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec 64 ______________________________________________________________________________________ sequence description registers 1 select voice filters 0x11 2 set adc level to 0db 0x18, 0x19 3 configure microphone gain 0x20, 0x21 4 set line output volume (if using) 0x1e, 0x1f 5 configure adc input mixer 0x22 6 configure micbias voltage 0x23 7 enable adc 0x26 8 enable lrclk and bclk (if operating in slave mode) n/a 9 enable max9880a 0x27 table 32. voice microphone record sequence description registers 1 select voice filters 0x11 2 set adc level to 0db 0x18, 0x19 3 configure microphone gain 0x20, 0x21 4 set line output volume (if using) 0x1e, 0x1f 5 configure adc input mixer 0x22 6 configure micbias voltage 0x23 7 enable adcs and dacs as required 0x26 8 enable lrclk and bclk (if operating in slave mode) n/a 9 enable max9880a 0x27 table 33. voice playback with record downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec ______________________________________________________________________________________ 65 sequence description register address register value 1 shdn = 0 0x27 04h 2 configure system clock 0x05 10h 3 configure dai2 clock 0x0b 60h 4 configure dai2 clock 0x0c 00h 5 configure dai2 audio path 0x0d 11h 6 configure dai2 audio path 0x0e 50h 7 select dac audio source 0x10 21h 8 select music filters 0x11 80h 9 set output volume (0db) 0x1c, 0x1d 09h 10 set line output volume (muted) 0x1e, 0x1f 40h 11 select headphone mode (output capacitorless mode) 0x24 02h 12 enable line outputs and dac as required 0x26 0ch 13 enable max9880a 0x27 84h table 34. music playback sequence description register address register value 1 shdn = 0 0x27 04h 2 configure system clock 0x05 10h 3 configure dai1 clock 0x0b 0fh 4 configure dai1 clock 0x0c 1fh 5 configure dai1 audio path 0x0d 04h 6 configure dai2 audio path 0x0e 30h 7 select dac audio source 0x10 21h 8 select voice gsm filters 0x11 33h 9 set adc level to 0db 0x18, 0x19 03h 10 configure microphone gain (20db preamp gain) 0x20, 0x21 54h 11 set headphone volume 0x1c, 0x1d 09h 12 set line output volume (if using) 0x1e, 0x1f 40h 13 configure adc input mixer 0x22 50h 14 configure micbias voltage (2.2v) 0x23 01h 15 select headphone mode 0x24 01h 16 enable line outputs, adc and dac as required 0x26 0bh 17 enable max9880a 0x27 84h table 35. voice duplex example of register settings for music playback and voice duplex senarios music playback f mclk = 12.288mhz (master clock supplied to codec), f lrclk = 48khz, standard i 2 s format, codec in slave mode, music source connected through s2 pins todai2 audio path, and output on headphone amplifiers (output capacitorless mode). voice duplex f mclk = 13mhz (master clock supplied to codec), f lrclk = 8khz, tdm/pcm format, codec in slave mode, voice signals on s1 pins to dai1 audio path andoutput on headphone amplifier left (differential mode). downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec 66 ______________________________________________________________________________________ mix vcm preg ref voice/audio filter digital audio path 1 (8khz to 48khz) pll1, ni1,regs 08-oa linear reg xtal osc xten, xtosc clock gen i 2 c/spi audio source selection sel1, sel2 adcl spdml mode adlen avflt voice/audio filter fm receiver mode avflt adren voice/audio filter mode, dvflt audio filter dcb mixspdml spdmdata voice/audio filter mode, dvflt mxinl pgaml: +20db to 0db palen: 0/20/30db 19(d7) 18 (c7) loutp hpmode loutn mix/mux mix adcr dgnd 47 (a1) pgnd 27 (e6, f6) agnd 15 (a8) mixinr pgamr: +20db to 0db paren: 0/20/30db ligl: +30db to 0db avl: +4db to -11db avlg: 0/6/12/18db avrg: 0/6/12/18db avr: +4db to -11db 1 f 1 f miclp/ digmicdata 1 f 13(c6) 2.2 f 10(b6) micbias micbias ref reg 17(b8) micln/ digmicclk micrp/ spdmdata spdmdata lnren linl micrn/ spdmclk 20(c8) 23(e8) lnlen ligr: +30db to 0db linr 24(f8) 21(d8) mix/mux vdacg: 0/6/12/18db dsts 39 (e1) 40 (e2) dvst: -9db to -69db _daca: 0db to -15db vdacg: 0/6/12/18db _daca: 0db to -15db voll: +6db to -84db logl: 0db to -30db volr: +6db to -84db mix/mux _daca: 0db to -15db voll: +6db to -84db _daca: 0db to -15db volr: +6db to -84db audio filter dcb hpmode 32 (e4) 31 (f4) x1x2 3 (a2) 4 (a3) routproutn headphone sense auxen 29 (e5) jacksns / aux 22 (d5) 30 (f5) lolen loutl logr: 0db to -30db 26 (e7) loren loutr 25 (f7) mix spdmr dac dac dalen daren mixspdmr mix 1b i/f mixdal mix mixdar mix 41 (d1) mclkbclks1 lrclks1 sdins1 sdouts1 2 (b3) scl/sclk 7 (a5) mode 8 (a4) 36 (f2) dvdds1 1.8v 37 (f1) 38 (d3) digital audio path 2 (8khz to 96khz) pll2, ni2,regs 0d-0f 44 (c2) 45 (c3) bclks2lrclks2 sdins2 sdouts2 42 (d2) 43 (c1) irq 6 (b5) dout 1 (b2) sda/din 5 (b4) cs spdmclk psclk freq1 1 f 16 (b7) micvdd 1.8v dvdd 1 f 46 (b1) 1.8v avdd 1 f 34 (e3, f3) 1.8v 1 f 9 (a6) 1.8v pvdd preg 1 f 12 (a7) spdmclk max9880a functional diagram/typical operating circuit downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec ______________________________________________________________________________________ 67 package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing per - tains to the package regardless of rohs status. package type package code outline no. land pattern no. 48 tqfn-ep t4866+1 21-0141 90-0057 48 wlp w482a3+1 21-0230 refer to application note 1891 downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec 68 ______________________________________________________________________________________ package information (continued) for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing per - tains to the package regardless of rohs status. downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec ______________________________________________________________________________________ 69 package information (continued) for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing per - tains to the package regardless of rohs status. downloaded from: http:///
max9880a low-power, high-performance dual i 2 s stereo audio codec maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 70 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 7/10 initial release 1 3/11 various data sheet errors 15C22, 24, 29, 31, 47, 49, 51, 52, 55C58, 60, 61, 62, 66 downloaded from: http:///

▲Up To Search▲

Price & Availability of MAX9880AETMT

	To Download MAX9880AETMT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .